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Circuits, Devices and Systems, IEE Proceedings -

Issue 5 • Date Oct 1997

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Displaying Results 1 - 10 of 10
  • Low-pass impedance transformation networks

    Publication Year: 1997 , Page(s): 284 - 288
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    Explicit formulas for the element values of a low-pass impedance transformation network having Butterworth or Chebyshev responses are given. For the second and the fourth-order networks, element values and transformation frequency band are directly determined by the impedance ratios. Since the expressions of the complex conjugate poles of the reflection coefficient of the network are rather concise, formulas for the higher order networks are obtained, thereby reducing the design of these networks to simple arithmetic and avoiding the use of design tables given by Matthaei (1964) and Cristal (1965) View full abstract»

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  • Differential register bank design for self timed differential bipolar technology

    Publication Year: 1997 , Page(s): 297 - 302
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    A high performance differential bipolar datapath based on the ARM architecture has been designed using `micropipeline' self-timed techniques. The datapath design included a full-custom 31×32 bit register bank. Traditional bipolar single-ended design techniques are not suited to implementing a RAM of this size on the target technology. This has led to the adoption of a fully differential circuit for the RAM cell here. The paper describes the challenges of designing such a differential register bank and the surrounding self-timed control. The data path has been fabricated by GEC Plessey Semiconductors and is fully operational. Results for the register bank are presented in terms of speed, power consumption and area View full abstract»

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  • High performance asynchronous FIR filter design in GaAs

    Publication Year: 1997 , Page(s): 289 - 296
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    An asynchronous FIR architecture design using a mixed mode logic approach in GaAs technology is presented. Combining an asynchronous design style with static and dynamic logic proves to be very suitable for high speed and low power implementation of real time mobile computing applications. The authors introduce a novel clocked dynamic latched (CDL) logic in GaAs to implement the micropipeline latches required in the single phase signalling. The reliable implementation of an 11-tap FIR filter in terms of speed, area and power dissipation in GaAs MESFET 0.6 μm Vitesse technology is demonstrated. This ASIC system is fully operative across the full range of process spread variations and the temperature range of 0 to 100°C. It is robust against power supply variations of 15% View full abstract»

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  • Properties and methods of calculating generalised arithmetic and adding transforms

    Publication Year: 1997 , Page(s): 249 - 258
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1020 KB)  

    The methods of generation of forward and inverse transformation kernels for generalised arithmetic and adding transforms are presented. Different methods of generation of transformation matrices or spectra in arbitrary polarities from a known transformation matrix or spectrum in some polarity have been developed. Using an optimised dyadic convolution process on the original data vector, a new method with a reduced number of operations is shown to calculate the generalised arithmetic and adding spectra. The properties and efficient ways of generation of permutation matrices used in the generation of arithmetic and adding transforms have been investigated. Based on the representation of transform matrices in the form of layered Kronecker matrices, a unified approach to the fast algorithms in terms of strand matrices has been developed. The computational complexities in the evaluation of arithmetic and adding spectral coefficients of an arbitrary order z and orders up to some z have been given View full abstract»

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  • Investigation of step-doped channel heterostructure field-effect transistor

    Publication Year: 1997 , Page(s): 309 - 312
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    A new heterostructure field-effect transistor (FET) with an InGaAs step-doped-channel (SDC) profile has been fabricated and demonstrated. The SDCFET studied provides the advantages of high current density, high breakdown voltage, wide gate voltage swing for high transconductance, and adjustable threshold voltage. A simple model is employed to analyse the performance of threshold voltage. For comparison two kinds of SDCFETs have been fabricated. For the 1×100 μm2 gated dimension, maximum drain saturation currents of 735 and 675 mA/mm, maximum transconductances of 200 and 232 mS/mm. Gate breakdown voltages of 15 and 12 V, wide gate voltage swing of 3.3 and 2.6 V with transconductance gm higher than 150 mS/mm, and threshold voltage -3.7 and -1.8 V are obtained, respectively. These good performance figures show the SDCFET has good potential for high-speed, high-power circuit applications View full abstract»

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  • Full-swing BiCMOS Schmitt trigger

    Publication Year: 1997 , Page(s): 303 - 308
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    A novel full swing BiCMOS Schmitt trigger, consisting of a BiCMOS inverter and a CMOS latch circuit, is proposed. This new circuit outperforms a conventional CMOS Schmitt trigger significantly. Even when the supply voltage is lowered down to 1.5 V, the new Schmitt trigger still maintains good operational quality. Based on the PSPICE simulations, the proposed BiCMOS circuit has less transmission delay and delay power product, as well as no static current under various supply voltages and output loads. The power consumption of the BiCMOS Schmitt trigger is actually slightly less than that of the CMOS counterpart. The circuit is also a full swing design. With these characteristics, this circuit is very suitable for high-speed and low-power applications View full abstract»

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  • Systolic arrays for the discrete Hilbert transform

    Publication Year: 1997 , Page(s): 259 - 264
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    A new fast parallel array algorithm to compute the discrete Hilbert transform for radix-2 length sequences is proposed. Unlike the existing fast methods which use transforms such as the fast Fourier transform, the proposed algorithm does not require the help of any fast transforms. This array algorithm offers a suitable expression for developing a VLSI systolic array for the discrete Hilbert transform. The authors propose one-dimensional and two-dimensional systolic architectures for the discrete Hilbert transform. The proposed architectures have the features of massive parallelism, high pipelining, regular data flow, modular nature and local interconnections. These arrays offer high speed computation of the discrete Hilbert transform for real-time signal processing applications View full abstract»

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  • Finite wordlength effects in two-dimensional multirate periodically time-varying filters

    Publication Year: 1997 , Page(s): 277 - 283
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    The effect of both input and product quantisation is examined for two's-complement, fixed-point arithmetic with rounding quantisation. Both direct-form and state-space structures are considered, and mathematical models for the transmission of the quantisation noise are established. Expressions are derived for the variance of the statistically-stationary output noise, with an example showing how a time-varying filter realisation could be superior to an equivalent time-invariant structure View full abstract»

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  • Current-mode defuzzifier circuit to realise the centroid strategy

    Publication Year: 1997 , Page(s): 265 - 271
    Cited by:  Papers (8)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    A current-mode circuit based on the square-rooter/multiplier and squarer/divider circuits to realise the centre-of-gravity defuzzification strategy is described. The current-mode approach allows it to operate at 3.3 V without degrading its dynamic range. The proposed circuit was fabricated in 0.8 μm single-polysilicon-double-metal CMOS technology, and the experimental results showed that it can operate at high speed with low power dissipation View full abstract»

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  • High-density 16/8/4-bit configurable multiplier

    Publication Year: 1997 , Page(s): 272 - 276
    Cited by:  Papers (7)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (756 KB)  

    A configurable serial-parallel multiplier based on Braun's and Baugh-Wooley's algorithms is presented. The multiplier can be configured to perform either signed or unsigned multiplications and to achieve variable precision. In this device one factor A(m) is fed serially with an arbitrary wordlength m while the other B(n) is stored in parallel with a configurable number of bits n=4, 8 or 16 bits. Switch elements are used to change the hardware connection between adjacent 4-bit multiplier basic blocks. This reconfiguration concept provides a higher precision multiplier by grouping adjacent cells or a higher throughput at low levels of precisions. A prototype of this multiplier has been fabricated using a full custom 1.0 μm CMOS technology. The active area contains 3450 transistors and occupies 0.47 mm2 corresponding to a very high gate density of 1532 gates/mm2 View full abstract»

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