By Topic

IEEE Transactions on Computers

Issue 7 • Jul 1988

Filter Results

Displaying Results 1 - 18 of 18
  • Fault tolerance in a systolic residue arithmetic processor array

    Publication Year: 1988, Page(s):886 - 890
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The regularity of systolic arrays and the potential for redundancy in residue number systems are used to provide fault tolerance in VLSI systems. The fault tolerance is concurrent with normal circuit operation and allows a continuous flow of correct data when a fault occurs. There is no interruption of valid data flow while the circuits are reconfigured. The technique also obviates the need for ul... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generating fractal-like surfaces on general purpose mesh-connected computers

    Publication Year: 1988, Page(s):882 - 886
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Realistic images of natural surfaces are often generated using computationally expensive stochastic modeling techniques. A parallel procedure to generate such models is presented. The target machines are general-purpose mesh-connected computers. The complexity of the procedure is similar to that of a proposed special-purpose parallel fractal generator View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An algebraic model for asynchronous circuits verification

    Publication Year: 1988, Page(s):835 - 847
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1116 KB)

    An algebraic methodology for comparing switch-level circuits with higher-level specifications is presented. Switch-level networks, `user' behavior, and input constraints are modeled as asynchronous machines. The model is based on the algebraic theory of characteristic functions (CF). An asynchronous automation is represented by a pair of CFs, called a dynamic CF (DCF): the first CF describes the p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Topological properties of hypercubes

    Publication Year: 1988, Page(s):867 - 872
    Cited by:  Papers (666)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    The n-dimensional hypercube is a highly concurrent loosely coupled multiprocessor based on the binary n-cube topology. Machines based on the hypercube topology have been advocated as ideal parallel architectures for their powerful interconnection features. The authors examine the hypercube from the graph-theory point of view and consider those features that make its connectivity ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An asynchronous, distributed flow control algorithm for rate allocation in computer networks

    Publication Year: 1988, Page(s):779 - 787
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    An asynchronous, distributed algorithm is presented that determines the optimal transmission rate allocation in computer networks with virtual circuit routing. The flow control problem is formulated as a gradient hill-climbing algorithm. It is distributed, since the entry node for each virtual circuit iteratively computes the rate allocation for that virtual circuit. The entry node communicates wi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Meaningful special classes of ternary logic functions-regular ternary logic functions and ternary majority functions

    Publication Year: 1988, Page(s):799 - 806
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Special ternary logic functions, namely, regular functions suitable for treating ambiguity and majority functions based on an extended majority principle are considered. The one-to-one correspondence between n-ary monotone regular ternary logic functions and (n+1)-ary monotone Boolean functions is investigated, as well as the one-to-one correspondence between n-ary monot... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient class of unidirectional error detecting/correcting codes

    Publication Year: 1988, Page(s):879 - 882
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A method for constructing a class of t-error correcting and all unidirectional error-detecting systematic codes is proposed. These codes have been shown to be more efficient than codes constructed using other methods proposed in the literature. In a special case, the code constructed is the Berger code View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance of ARQ schemes on token ring networks

    Publication Year: 1988, Page(s):826 - 834
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    Token ring networks differ in the manner in which acknowledgements are handled. In Newhall rings, acknowledgements of data packets are either sent as independent packets or piggybacked on returned data packets. In acknowledgement rings, there is an acknowledgement field in each data packet. The authors present an empirical formula that predicts the average network access delay in networks where th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Strongly fault secure PLAs and totally self-checking checkers

    Publication Year: 1988, Page(s):863 - 867
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A general approach is presented to the design of totally self-checking (TSC) programmable logic arrays (PLAs). A strongly fault secure (SFS) implementation is suggested for the functional PLA, which is shown to be SFS whenever the output is encoded by two-rail code. K-unit TSC checker (TSCC) element are defined to construct TSC checkers. The TSCC is very appropriate for the companion of t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sorting large files on a backend multiprocessor

    Publication Year: 1988, Page(s):769 - 778
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    The authors investigate the feasibility and efficiency of a parallel sort-merge algorithm by considering its implementation of the JASMIN prototype, a backend multiprocessor built around a fast packet bus. They describe the design and implementation of a parallel sort utility and present and analyze the results of measurements corresponding to a range of file sizes and processor configurations. Th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Communication performance in multiple-bus systems

    Publication Year: 1988, Page(s):848 - 853
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    A simple queueing model is presented for studying the effect of multiple-bus interconnection networks on the performance of asynchronous multiprocessor systems. The proposed model is suitable for systems in which each processor has a local memory and is thus able to continue processing while waiting for a response from the global memory. An approximate, closed-form solution is given that is simple... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An experimental study to determine task size for rollback recovery systems

    Publication Year: 1988, Page(s):872 - 877
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The effects of using a recovery cache to save the variables of a program are studied. A novel optimization model for rollback is formulated to include the effects of a recovery cache in rollback systems. The parameters of the model proposed are the maximum recovery time, the cache size, and the save and load time associated with the task size. The results are also discussed of an experimental stud... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault tolerance capabilities in multistage network-based multicomputer systems

    Publication Year: 1988, Page(s):788 - 798
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1124 KB)

    The inherent fault tolerances of systems based on nonredundant multistage interconnection networks (MINs) is investigated. Graph models are used to describe the system, indicate faults, study their effects, and aid in mathematical formulation of these effects. Methodical terminology for defining functionality of two-sided-MIN-based multicomputer systems and specifying their fault tolerance of such... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient design of totally self-checking checkers for all low-cost arithmetic codes

    Publication Year: 1988, Page(s):807 - 814
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    A method is proposed that is based on the partitioning of the input code variables into two sections, each section representing the binary form of a number Z1 and Z2, respectively. For a code with check base A =2m-1, two m-bit end-around carry adder trees calculate the modulo m residue of Z1 and ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Failure dependent bandwidth in shuffle-exchange networks

    Publication Year: 1988, Page(s):853 - 858
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A failure-dependent bandwidth model for shuffle-exchange (S/E) and augmented shuffle-exchange (S/E+) interconnection networks is presented. The models are based on probabilities of either data or address model failures for the individual binary switches that comprise the network and give the expected bandwidth as a function of the probability of failures in these switches. A model consistent with ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient complex matrix multiplication

    Publication Year: 1988, Page(s):877 - 879
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    A well-known algorithm for complex multiplication which requires three real multiplications and five real additions is observed not to require commutativity. The resulting extension of its applicability to complex matrices is examined. The computational savings are shown to approach 1/4. even if a real multiplication is not more computationally costly than a real addition. The computational cost f... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Stochastic high-level Petri nets and applications

    Publication Year: 1988, Page(s):815 - 825
    Cited by:  Papers (56)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (924 KB)

    A class of stochastic Petri nets called stochastic high-level Petri nets (SHLPNs) is proposed. SHLPNs are high-level Petri nets augmented with exponentially distributed firing times. SHLPNs generally lead to models with a smaller state space. A computer marking concept is introduced that allows a considerable reduction of the number of states and induces a correct grouping of states in the Markov-... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Floating-point to logarithmic encoder error analysis

    Publication Year: 1988, Page(s):858 - 863
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The logarithmic number (LNS), which supports high-speed, high-precision arithmetic, is envisioned as a possible arithmetic coprocessor attachment to a floating-point (FLP) processor. An error analysis of an FLP-to-LNS encoder is presented. Analytic expressions for the probability density function of the encoding error are derived for a number of cases, according to the memory word lengths used for... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org