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Computers and Digital Techniques, IEE Proceedings E

Issue 5 • Date Sep 1989

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Displaying Results 1 - 17 of 17
  • Test generation of C-testable array dividers

    Page(s): 434 - 442
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    With respect to the regular and iterative structure of iterative logic arrays (ILAs), the C-testable design that can be tested with a set of constant length irrespective of the circuit size has been presented. In the paper the concept of C-testability developed for ILAs is applied to the design of C-testable array dividers. The results show that the proposed nonrestoring and restoring array dividers are C-testable and can be fully tested using only 20 and 40 test patterns, respectively, irrespective of the array size. The innovative feature of the proposed test-generation scheme is that the generated patterns are constructed by repetitive and simple patterns that can be easily produced by a set of labels. Algorithms that generate the test patterns and expected outputs are also provided in detail. View full abstract»

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  • Content-addressable memories applied to execution of logic programs

    Page(s): 383 - 388
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    The paper describes a number of techniques for using content-addressable memory to speed up the execution of logic programs for both single and multiple processor implementations. The techniques shown allow for significant speedups in unification, clause selection, branch switching, variable handling and garbage collection. For multiple processor implementations, the literal ordering and environment join algorithms are also improved. In addition to the speed improvements, some simplification of software results from performing indexing operations in content-addressable memory. View full abstract»

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  • Very fast reduction machine for functional programming without variables

    Page(s): 443 - 449
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    The paper presents a new programming language and its reduction machine. The name of the language is Graal and it is based on the unusual concepts of functional form issued from FP systems and uncurryfied combinator from combinatory logic. It does not use variables but is nevertheless readable. Its reduction machine is new, object-oriented, distributed and modular. It runs very efficiently on classical Von Neumann architectures and can be used to implement other functional languages. View full abstract»

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  • Detection of stuck-at and bridging faults in Reed-Muller canonical (RMC) networks

    Page(s): 430 - 433
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    Boolean function realisations by Reed-Muller networks have many desirable properties in terms of testability. In the paper it is shown that there exists a single set of test patterns which would detect all single stuck-at and all single bridging (short-circuit) faults in Reed-Muller networks, and the number of test patterns is shown to be at most 3n+5, where n is the number of input variables in the function. In the case of networks with k outputs, where kn, the number of test patterns required to detect all single stuck-at and all single detectable bridging faults (both AND and OR) is also shown to be 3n+5. View full abstract»

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  • Neural networks and conditional association networks: common properties and differences

    Page(s): 343 - 350
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (660 KB)  

    At first it is shown how large networks can be represented in an illustrative way. Then, the special aspects of neural networks are discussed. When conditional association arrays and semantic memories are plotted as networks surprising similarities arise, but important characteristic differences can be seen too. The first experiments suggest that substantial progress in text processing may be achieved faster with conditional association networks than with neural networks. View full abstract»

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  • Architectures for testability and fault tolerance in content-addressable systems

    Page(s): 366 - 373
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    For the next computer generation, which may have extensive artificial intelligence properties, the use of associative processing may have increasing importance. VLSI technologies especially can stimulate the development of larger content-addressable memories (CAMs). The problem of production yield and component failure, as well as that of efficient testability, will be as important as for other computer components. Therefore, compared with conventional random access memory, the more complicated memory structure of CAMs has greater problems of testing and reconfigurability. In the paper, the problems of testability and fault tolerance in different CAMs and content-addressable processor systems are discussed. View full abstract»

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  • Control of manipulators by neural networks

    Page(s): 395 - 399
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    One of the most intriguing properties of natural neural systems is their ability to control exceedingly sophisticated manipulators like arms, legs or trusses, i.e. to produce a large number of efficient motor commands in real time. This remarkable capability of neural systems is based on parallel information processing. The concepts of parallel information processing are not very well understood, mainly because they differ fundamentally from the algorithmic concepts of sequential information processing prevalent in contemporary computers. View full abstract»

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  • Integrating voice and data services in token rings

    Page(s): 456 - 463
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    An access protocol for efficient voice-data integration in a token ring network is described. It is based on the adoption of a variable size of voice packet that is determined by the actual load conditions. To take into account efficiency problems of token rings related to the ratio of average packet size and ring latency, two versions of the access protocol are described that adopt different token releasing strategies, namely, single-token and multiple-token. In each of these protocols, vice and data users are serviced according to a specific priority scheme, which bounds voice packet delay and guarantees a minimum data bandwidth fairly allocated among data stations. View full abstract»

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  • Design of an associative processor array

    Page(s): 374 - 382
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    The architecture of a new associative processor array chip, working name GLiTCH, is described and details are given of the techniques used in its VLSI design. The low-level operating characteristics of the chip are explained. A number of system configurations are explored and finally the use of GLiTCH in a vision processing module, currently being designed, is described. View full abstract»

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  • Bidirectional ring-based termination detection algorithms for distributed computations

    Page(s): 415 - 422
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    An interesting and difficult problem in the area of distributed problem solving is that of detecting the termination of distributed programs soon after their assigned task is over. In a distributed environment, processes of a distributed program communicate only through exchange of messages and no process maintains complete information about the state of other processes. Additional efforts are, therefore, required to detect the situation when the processes of a distributed program complete their assigned task. The problem of detection of such a situation was first brought into prominence by N. Francez (1980). The problem requires taking snapshots over the states of the processes and then testing the termination criterion over these states. So far, reported algorithms can be broadly categorised into classes depending upon the topology employed namely a unidirectional ring, a spanning tree, and an arbitrary network. The authors explore yet another alternative in the form of bidirectional control communication around a ring. This type of communication potentially offers selective advantages of all the earlier approaches and depicts an approach lying between unidirectional communication and communication in all directions. View full abstract»

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  • ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters

    Page(s): 450 - 455
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    The parallel/serial test procedure for application-specific integrated circuit (ASIC) logic surrounding embedded asynchronous counters is proposed, which increases counter controllability and observability and reduces test sequence length. Optimisation of counter partitioning and test sequence generation is carried out with the CAD program COUNTESS. For optimal partitioning COUNTESS calculates both the test hardware overhead and the minimum number of test cycles. View full abstract»

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  • Fault tolerance of neural associative memories

    Page(s): 389 - 394
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    The effects of hardware limitations and fabrication faults on the fault tolerance of neural associative memories using the Hopfield interconnect topology are investigated. It is shown that neural computing structures are not by definition fault tolerant, and that the degree of tolerance is very sensitive to the assumed physical fault model and to the nature of the stored information. View full abstract»

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  • Windmill pn-sequence generators

    Page(s): 401 - 404
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    A windmill generator is a high-speed sequence generator capable of producing blocks of nu consecutive symbols in parallel. It consists of nu feedback-shift registers linked into a ring. The sequences are identical to those produced by a linear feedback-shift register with feedback polynomial of the special ('windmill') form f(t)= alpha (tnu )-tL beta (t- nu ), where alpha (t) and beta (t) are polynomials of degree less than L/ nu . L (relatively prime to nu ) is the degree of the polynomial, and is also the sum of the lengths of the registers making up the windmill. The connections of the windmill generator are directly specified by the coefficients of alpha (t) and beta (t). The polynomial f(t) must be primitive if the output sequence is to be of maximal period. The authors have devised a search for windmill polynomials over the binary field that can generate sequences of period 2L-1 in blocks of size nu =4, 8, and 16, for L ranging over the odd values from 7 to 127. When L identical to +or-3 mod 8, no irreducible windmill polynomials at all were found. For the other odd values of L, primitive windmill polynomials seem to occur about twice as frequently as would be expected from probabilistic considerations, so that they are in fact very common. For such values of L, roughly 2/L of all windmill polynomials with given nu appear to be primitive. View full abstract»

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  • Pruned-trellis search technique for high-rate convolutional codes

    Page(s): 405 - 414
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    A new method to search for high-rate convolutional codes is achieved by means of a pruned trellis. This makes possible a reduced search procedure that can not be accomplished by standard methods. This new search technique makes use of the concept of the expanded column distance function of a convolutional code. By use of this search procedure, codes are found with an optimum distance profile followed by a maximisation of dfree. A number of systematic convolutional codes of high rates 3/4, 4/5, 5/6, 6/7 and 3/5 are found and listed in this paper. View full abstract»

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  • Performance analysis of queuing networks with end-to-end window flow control

    Page(s): 423 - 429
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    The paper deals with queuing networks with window flow control and group arrivals. By using the method of entropy maximisation, an equivalent arrival process is obtained and is then applied to study queuing networks. The authors consider the networks of single-server nodes in both continuous and discrete time, and multiple exponential-server nodes in continuous time. Numerical results are obtained for the mean number of packets at the nodes, the server utilisations and the network throughput. It is shown that the calculated results agree favourably with the simulation results. View full abstract»

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  • Content-addressable mass memories

    Page(s): 351 - 356
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    In the area of non-numerical data processing, the usual local addressing with its fixed access path is troublesome and time-consuming if very large data sets have to be handled. Next to the well-known software procedures more and more hardware solutions are sought for supporting the typically content-addressable data access. The apparently ideal solution of a parallel associative memory cannot be implemented in the capacities of mass memories, but it can be substituted for mass memories with content addressability. View full abstract»

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  • Flag-algebra: a new concept for the realisation of fully parallel associative architectures

    Page(s): 357 - 365
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (951 KB)  

    The paper describes a new concept for the design of parallel-working associative memory and processor architectures, which is able to process arithmetical operations as well as complex search-operations for the sets of data in parallel. The proposed concept is based on a transformation method. It maps a set of word-oriented data into flag-oriented data. Each word of the set is represented by a flag in a flagvector. The position of a flag in the flagvector is defined by the transformation and corresponds to the value of the transformed word. To obtain parallelism for various operations, the flags of the flagvector are processed simultaneously. The result of these operations is also flags. They can be retransformed to word-oriented data. A new algebra called flag-algebra to investigate operations on the flagvector is introduced. This algebra is the isomorph to the set-theory and Boolean algebra. The most important axioms and laws of calculation in this algebra are described. They can be seen as a substantial basis for the development of flag-oriented hardware systems. Based on this algebra, the architecture of an associative monoprocessor is presented to process arithmetical as well as complex search operations in parallel. Furthermore, some languages adequate for this architecture and the performance of the processor is discussed. View full abstract»

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