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IEE Proceedings E - Computers and Digital Techniques

Issue 5 • Date Sep 1989

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Displaying Results 1 - 17 of 17
  • Test generation of C-testable array dividers

    Publication Year: 1989, Page(s):434 - 442
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (556 KB)

    With respect to the regular and iterative structure of iterative logic arrays (ILAs), the C-testable design that can be tested with a set of constant length irrespective of the circuit size has been presented. In the paper the concept of C-testability developed for ILAs is applied to the design of C-testable array dividers. The results show that the proposed nonrestoring and restoring array divide... View full abstract»

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  • Detection of stuck-at and bridging faults in Reed-Muller canonical (RMC) networks

    Publication Year: 1989, Page(s):430 - 433
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (312 KB)

    Boolean function realisations by Reed-Muller networks have many desirable properties in terms of testability. In the paper it is shown that there exists a single set of test patterns which would detect all single stuck-at and all single bridging (short-circuit) faults in Reed-Muller networks, and the number of test patterns is shown to be at most 3n+5, where n is the number of input variables in t... View full abstract»

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  • Windmill pn-sequence generators

    Publication Year: 1989, Page(s):401 - 404
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (356 KB)

    A windmill generator is a high-speed sequence generator capable of producing blocks of nu consecutive symbols in parallel. It consists of nu feedback-shift registers linked into a ring. The sequences are identical to those produced by a linear feedback-shift register with feedback polynomial of the special ('windmill') form f(t)= alpha (tnu )-tL beta (t- nu ), wher... View full abstract»

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  • Integrating voice and data services in token rings

    Publication Year: 1989, Page(s):456 - 463
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (736 KB)

    An access protocol for efficient voice-data integration in a token ring network is described. It is based on the adoption of a variable size of voice packet that is determined by the actual load conditions. To take into account efficiency problems of token rings related to the ratio of average packet size and ring latency, two versions of the access protocol are described that adopt different toke... View full abstract»

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  • Performance analysis of queuing networks with end-to-end window flow control

    Publication Year: 1989, Page(s):423 - 429
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (464 KB)

    The paper deals with queuing networks with window flow control and group arrivals. By using the method of entropy maximisation, an equivalent arrival process is obtained and is then applied to study queuing networks. The authors consider the networks of single-server nodes in both continuous and discrete time, and multiple exponential-server nodes in continuous time. Numerical results are obtained... View full abstract»

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  • Content-addressable mass memories

    Publication Year: 1989, Page(s):351 - 356
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (580 KB)

    In the area of non-numerical data processing, the usual local addressing with its fixed access path is troublesome and time-consuming if very large data sets have to be handled. Next to the well-known software procedures more and more hardware solutions are sought for supporting the typically content-addressable data access. The apparently ideal solution of a parallel associative memory cannot be ... View full abstract»

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  • Control of manipulators by neural networks

    Publication Year: 1989, Page(s):395 - 399
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (576 KB)

    One of the most intriguing properties of natural neural systems is their ability to control exceedingly sophisticated manipulators like arms, legs or trusses, i.e. to produce a large number of efficient motor commands in real time. This remarkable capability of neural systems is based on parallel information processing. The concepts of parallel information processing are not very well understood, ... View full abstract»

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  • ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters

    Publication Year: 1989, Page(s):450 - 455
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (348 KB)

    The parallel/serial test procedure for application-specific integrated circuit (ASIC) logic surrounding embedded asynchronous counters is proposed, which increases counter controllability and observability and reduces test sequence length. Optimisation of counter partitioning and test sequence generation is carried out with the CAD program COUNTESS. For optimal partitioning COUNTESS calculates bot... View full abstract»

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  • Bidirectional ring-based termination detection algorithms for distributed computations

    Publication Year: 1989, Page(s):415 - 422
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (700 KB)

    An interesting and difficult problem in the area of distributed problem solving is that of detecting the termination of distributed programs soon after their assigned task is over. In a distributed environment, processes of a distributed program communicate only through exchange of messages and no process maintains complete information about the state of other processes. Additional efforts are, th... View full abstract»

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  • Architectures for testability and fault tolerance in content-addressable systems

    Publication Year: 1989, Page(s):366 - 373
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (648 KB)

    For the next computer generation, which may have extensive artificial intelligence properties, the use of associative processing may have increasing importance. VLSI technologies especially can stimulate the development of larger content-addressable memories (CAMs). The problem of production yield and component failure, as well as that of efficient testability, will be as important as for other co... View full abstract»

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  • Neural networks and conditional association networks: common properties and differences

    Publication Year: 1989, Page(s):343 - 350
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (660 KB)

    At first it is shown how large networks can be represented in an illustrative way. Then, the special aspects of neural networks are discussed. When conditional association arrays and semantic memories are plotted as networks surprising similarities arise, but important characteristic differences can be seen too. The first experiments suggest that substantial progress in text processing may be achi... View full abstract»

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  • Fault tolerance of neural associative memories

    Publication Year: 1989, Page(s):389 - 394
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (572 KB)

    The effects of hardware limitations and fabrication faults on the fault tolerance of neural associative memories using the Hopfield interconnect topology are investigated. It is shown that neural computing structures are not by definition fault tolerant, and that the degree of tolerance is very sensitive to the assumed physical fault model and to the nature of the stored information. View full abstract»

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  • Very fast reduction machine for functional programming without variables

    Publication Year: 1989, Page(s):443 - 449
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (568 KB)

    The paper presents a new programming language and its reduction machine. The name of the language is Graal and it is based on the unusual concepts of functional form issued from FP systems and uncurryfied combinator from combinatory logic. It does not use variables but is nevertheless readable. Its reduction machine is new, object-oriented, distributed and modular. It runs very efficiently on clas... View full abstract»

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  • Pruned-trellis search technique for high-rate convolutional codes

    Publication Year: 1989, Page(s):405 - 414
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (684 KB)

    A new method to search for high-rate convolutional codes is achieved by means of a pruned trellis. This makes possible a reduced search procedure that can not be accomplished by standard methods. This new search technique makes use of the concept of the expanded column distance function of a convolutional code. By use of this search procedure, codes are found with an optimum distance profile follo... View full abstract»

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  • Design of an associative processor array

    Publication Year: 1989, Page(s):374 - 382
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (676 KB)

    The architecture of a new associative processor array chip, working name GLiTCH, is described and details are given of the techniques used in its VLSI design. The low-level operating characteristics of the chip are explained. A number of system configurations are explored and finally the use of GLiTCH in a vision processing module, currently being designed, is described. View full abstract»

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  • Content-addressable memories applied to execution of logic programs

    Publication Year: 1989, Page(s):383 - 388
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (512 KB)

    The paper describes a number of techniques for using content-addressable memory to speed up the execution of logic programs for both single and multiple processor implementations. The techniques shown allow for significant speedups in unification, clause selection, branch switching, variable handling and garbage collection. For multiple processor implementations, the literal ordering and environme... View full abstract»

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  • Flag-algebra: a new concept for the realisation of fully parallel associative architectures

    Publication Year: 1989, Page(s):357 - 365
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (951 KB)

    The paper describes a new concept for the design of parallel-working associative memory and processor architectures, which is able to process arithmetical operations as well as complex search-operations for the sets of data in parallel. The proposed concept is based on a transformation method. It maps a set of word-oriented data into flag-oriented data. Each word of the set is represented by a fla... View full abstract»

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