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Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Issue 3 • Date Aug. 1997

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Displaying Results 1 - 22 of 22
  • 5th Topical Meeting On Electrical Performance Of Electronic Packaging

    Page(s): 0_1
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  • Performance analysis of MCM systems

    Page(s): 334 - 341
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    When a new interconnection technology is developed, it is of interest to accurately characterize its electrical features from a system's perspective and evaluate its possible application areas and boundary limits. Accurate design models can then be extracted and used for a correct design and implementation of electronic systems. This paper describes a case study used to characterize a five-layer thin-film multichip module (MCM) technology developed for high speed digital applications. The high frequency characterization of the substrate has been combined with the electrical models of the input/output (I/O) buffers of a complementary metal-oxide-semiconductor (CMOS) technology to accurately analyze the signal propagation with a network simulation tool. A test chip and MCM module have been developed to evaluate how the maximum system frequency is influenced by different quantities such as line length, type of driver or noise. Experimental results, showing a good match with simulations, demonstrate the effectiveness of this approach. It is also shown how it is possible to take advantage of some apparently limiting features of thin-film MCM's to actually improve the system performance View full abstract»

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  • Highly efficient coupling between single-mode fiber and polymer optical waveguides

    Page(s): 225 - 228
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    Single-mode optical D-fiber is fabricated and coupled to single-mode acrylic waveguides by use of a novel technique utilizing alignment ways and a transcision. The D-fiber is fabricated by lapping the cladding layer of a single-mode fiber to the core. Optical waveguides and alignment ways are made with polymers by photolithography. This technique allows coupling of the optical elements by means of a transcision placed perpendicularly to the optical axis of the waveguide in order to achieve efficient coupling of single-mode fiber to optical waveguides with typical coupling losses of 0.5±0.2 dB with index matching liquid. The technique also allows for passive coupling resulting in an excess loss over active alignment of 0.35 dB. Coupling efficiency results presented here are the highest for single-mode fiber to single-mode optical waveguide. The best coupling produced an efficiency of 97.3% (or 0.12 dB loss) View full abstract»

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  • Cost-effective multichip module manufacture using passive substrate fault tolerance

    Page(s): 320 - 326
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    The widespread use of multichip module (MCM) technology is currently restricted by high substrate cost, poor substrate yield and low quality level of mounted components: the known good die (KGD) problem. This paper examines three yield enhancing fault tolerance techniques suitable for use with conventional (passive) substrates with the aid of a generic processor-memory MCM architecture. The use of spare memory dies and a paged address space is shown to be a very effective solution to the KGD problem for this particular architecture View full abstract»

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  • Low-cost fabrication of optical subassemblies

    Page(s): 256 - 263
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    The optical subassembly is a major contributor to the cost of a fiberoptic computer data link. A technology for low-cost fabrication of optical subassemblies is described, with emphasis on a transmitter subassembly designed for fiber-channel standard operation (266 Mb/s for 2 km; 1063 Mb/s for 500 m). A factor of three cost reduction is achieved by limiting the parts count to only three: a laser or receiver chip packaged in a TO-can, a plastic housing, and a plastic aspheric lens; and by employment of a fast, automated active-alignment and subsequent fixing technique. Key enabling features include the use of precision injection molding of specially chosen plastics, an aspheric lens design which permits wide positional variations in the axial direction, and curing of a fast setting epoxy through the use of RF power. A tool was constructed which produced subassemblies at high yield having satisfactory performance View full abstract»

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  • Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA

    Page(s): 266 - 271
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    This paper presents the simultaneous switching noise (SSN) measurements, modeling, and simulation of a flip-chip complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) test chip on a multilayer ceramic ball grid array (CBGA) package. Technology and design features of the chip and package test vehicles are described. Time-domain noise measurement techniques and results are presented in detail. Circuit modeling and simulation methodologies are developed and validated by strong correlation between measurement and simulation results View full abstract»

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  • Wetting interactions between the Ni-Cu-P deposit and In-Sn solders

    Page(s): 211 - 216
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    The interactions during wetting between an electroless Ni-Cu-P deposit and molten InSn solders were investigated with the aid of scanning electron microscope (SEM), X-ray diffractometer (XRD), and Auger electron spectroscope (AES). The intermetallics In3Ni 2 and In27Ni10 were formed at the interlayer for the Ni-Cu-P with 51In-49Sn and 80In-20Sn systems, in the temperature range of 250-300°C. In addition to these two intermetallic compounds Ni3Sn4 was also formed with the 20In-80Sn system. The Ni3Sn4 dissipates gradually with increasing temperature. A two-stage wetting mechanism was disclosed for the wetting of Ni-Cu-P deposit with the InSn solders in the temperature range of 250-325°C View full abstract»

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  • Criteria for the assessment of reliability models

    Page(s): 229 - 234
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    Reliability predictions are often used as the basis for important business decisions, including parts selection, environmental controls, qualification plans, warranties, maintenance plans, and spare requirements. Before a production can be trusted for use, especially in applications requiring high reliability and safety, it must be carefully assessed for validity. In other words, reliability models should only be employed once they are judged to be reliable themselves. It is thus imperative that they satisfy an established set of assessment criteria before being applied to electronic products. This paper establishes the minimum criteria needed to assess the value of a reliability model. The criteria emphasize the influence of environmental and operational stresses; variabilities in failure mechanisms, modes, and sites; design parameters; manufacturing processes and defects; and the statistical distribution of failures. If a model satisfies the criteria, it can be certified as robust enough to provide competent assessments. As an example, the criteria are used to assess various microcircuit reliability models View full abstract»

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  • Residual stresses in plastic IC packages during surface mounting process preceded by moisture soaking test

    Page(s): 247 - 255
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    In the present study, moisture and temperature distributions and residual stresses in plastic encapsulated integrated circuit (IC) packages are evaluated in order to assess product reliability. Finite element analyses are utilized to calculate hygro-thermally induced deformations and stresses in plastic IC packages during the surface mounting process preceded by the moisture soaking test. Residual stresses developed in thin lead-on-chip (LOG) thin small outline packages (TSOP) during the reflow soldering process preceded by the 168 h 85°C/85% RH moisture soaking test have been studied. Numerical results showed that substantially high positive stresses σz arose in the silicon chip and the leadframe while negative stresses were observed in the encapsulant below the chip when TSOP packages were exposed to the reflow soldering process. Such opposite stress development in the silicon chip and encapsulant below the chip may result in the delamination and popcorn crack. The results also showed that the magnitude of residual stresses in IC packages depended not only on the magnitude of loading but also on the loading history due to the hygro-thermo-viscoelastic behavior of plastic mold compound materials View full abstract»

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  • SSO noise electrical performance limitations for PQFP packages

    Page(s): 292 - 297
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    Factors which affect the simultaneous switching output (SSO) noise electrical performance of plastic quad flat pack (PQFP) packages are discussed in this paper. Limitations on PQFP package design for SSO noise are presented, along with a methodology for extracting the effective inductance limits for PQFP packages View full abstract»

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  • Versatile multilayer MCM-D structure for high reliability applications

    Page(s): 327 - 333
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    Within the joint European submicron silicon initiative (JESSI) project Silicon Hybrids, Industrial Microelectronics Center (IMC) has developed and MIL-std 883 B qualified a highly versatile thin film structure suitable for high reliability MCM applications. The basis is a four-layer structure with aluminum conductors and benzocyclobutene (BCB) dielectric formed on a 5" silicon wafer. Optionally, a solderable top layer of Ni and Au ran be added for flip chip assembly, and passive components can be integrated simply by adding a SiCr and a SiOx Ny layer beneath the four-layer structure. To achieve a mechanically stable structure, a good understanding is required of how different parameters, such as conductor and dielectric material, and layer structure and dimensions affect the final result. The evaluation has been focused on mechanical stresses due to thermal cycling and shock. Finite Element Analysis and Scanning Electron Microscopy have been utilized in the evaluation. The results show that good adhesion between the different layers, careful stress control in the materials, and metal thickness dependent restrictions in the design rules are necessary to pass the MIL-std tests. With increasing demands on system integration, performance and low production cost, flip chip mounting of dies has become an attractive technology. For flip chip assembly, the chips often have solder balls, whence the substrates must have solderable assembly pads. However, all chips are not available with solder balls, and in these cases solder balls must be applied either to the chip or the substrate, IMC has developed a process to produce solder balls with well-controlled thickness and composition for flip chip assembly on Si substrates View full abstract»

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  • Impedance and crosstalk of stripline and microstrip transmission lines

    Page(s): 217 - 224
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    Signal conductors between two ground planes (i.e.. stripline transmission lines) and signal conductors above one ground plane (i.e., microstrip transmission line) serve as the means for propagating high-speed digital and analog signals on printed wiring boards (PWBs), and multichip modules (MCMs). For many important applications (e.g., wireless and other high speed technologies), the need for miniaturization requires that these high-speed electrical interconnections be provided on relatively dense PWBs and MCMs. This leads to design uncertainties concerning characteristic impedance and especially crosstalk. The purpose of this paper is to develop relatively simple formulas for computing the characteristic impedances and crosstalk of coupled stripline and microstrip transmission lines. Both unbalanced and balanced transmission lines are treated. The new formulas apply to both rectangular and circular conductors and are expressed in terms of the physical dimensions of the conductors and the effective dielectric constant of the medium. The formulas yield results which agree well with known results and experimental results View full abstract»

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  • Early analysis of cost/performance trade-offs in MCM systems

    Page(s): 308 - 319
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    This paper explores early analysis of the complex relationships between system architectures and the active and packaging materials from which they are implemented. The goals of this analysis are to enable the designer to specify cost effective technologies for a particular system, and to uncover resources which may be exploited to increase performance of such a system, early in the design process. We describe a prototype tool called IMPACT, which will predict cost, performance, power, and reliability, and present several case studies demonstrating its use View full abstract»

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  • Testability and signal integrity in a low cost multichip module

    Page(s): 300 - 307
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    The design process for low-cost multichip modules (MCM's) is presented. Modifications to the design are often made in order to increase testability. Some of these modifications can degrade signal integrity, however. The important aspects to consider in order to make rational design tradeoffs are presented. Test strategies and techniques are discussed. The effects on signal quality of additional test stubs to the internal nets of the MCM are analyzed. It is shown that the addition of unplanned test stubs can degrade the signal pulse quality and any such additions must require further signal integrity analysis View full abstract»

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  • Power distribution fidelity of wirebond compared to flip chip devices in grid array packages

    Page(s): 272 - 278
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    We have simulated the power fidelity of wirebond and flip chip grid array packages suitable for next generation microprocessors. The dc power droop across the chip from resistive losses and the ac power noise from switching events were studied as a function of the number of package power planes, dielectric constant, the number of chip connections, decoupling capacitors, and their location. Simulation program with integrated circuit emphasis (SPICE) was used to simulate the effects of the package and printed wiring board (PWB) characteristics on the differential power supply noise. We varied the number of package power planes, their dielectric constant, and the use of discrete decoupling capacitors and capacitor location with a goal of finding the best low cost design for effective power delivery to the chip View full abstract»

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  • High density packaging of X-band active array modules

    Page(s): 279 - 291
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    A new high-density package design has been used to reduce the cost, weight, and size of X-band active array radars. The package used multilayer aluminum nitride (AlN) substrates, flipped monolithic microwave integrated circuit (MMIC) chips, coplanar waveguide transmission lines, and solderless fuzz button interconnects. This paper discusses the design tradeoffs, the package construction and assembly, and test results View full abstract»

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  • S parameter-based experimental modeling of high Q MCM inductor with exponential gradient learning algorithm

    Page(s): 202 - 210
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    Lumped inductors are very desirable passive components in wireless/RF circuits integrated on multichip module (MCM) substrates. This paper models the inductor by using on-wafer high frequency measurement, S parameter formulation and exponential gradient optimization method. A new equivalent circuit model including both lumped and distributed effects is proposed. Both the magnitudes and phases of all S parameters fit well for all the inductors we built. It is shown that the most effective way to increase the quality factor is to use a high resistivity substrate. The resulting experimental model provides a solid measurement-verified ground for circuit design and numerical characterization View full abstract»

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  • Effects of scanning and biasing circuit restructuring on the response of a large area magnetic field sensor array

    Page(s): 342 - 348
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    A large area magnetic field sensor array (LAMSA) has been designed and fabricated with built-in redundancy to achieve higher yield. The laser-link technology is used as the restructuring tool. The sensor system response is measured and calibrated with a general regression analysis method. Using the same method, an algorithm to evaluate the effects of the restructuring schemes of the biasing and scanning circuits on the response is developed. From measurements taken before and after restructuring, the influence of the row and the column scanning circuits restructuring are found to be weak, provided the resistance values of the formed laser-links are low, especially in the case of the column scanning circuit. Restructuring of the cascode current mirror acting as active load has shown the close dependence of the sensor cell responses on the transistor parameters. Helped by these restructuring schemes, the initial yield of 23 tested chips of size 6×3 mm was raised from 39 to 61% View full abstract»

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  • VCSEL electrical packaging analysis and design guidelines for multi-GHz applications

    Page(s): 191 - 201
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    The introduction of the vertical cavity surface emitting laser (VCSEL) diode structure has created the need for enhanced performance, low cost, optical packages capable of supporting data rates as high as 5 Gb/s. The popular laser packages, such as the TO-46 and the TO-56 “cans”, which have been traditionally used for edge emitting laser diodes at much lower frequencies, cannot support this dramatic increase in data rates. Package parasitics and severe impedance discontinuities, inherent in the TO-46 and TO-56, impose stringent frequency limitations and dramatically effect the integrity of the electrical signals. Because electrical waveform control is essential for proper laser diode operation, these high frequency performance problems must be identified and overcome. This paper will describe electromagnetic and SPICE modeling techniques which were used to create equivalent circuits of the TO-36 and the TO-56 cans for comparison to measured results to achieve model verification. Subsequently, the models were used to determine frequency limitations associated with the TO-46 and the TO-56 laser cans. Additionally, the specific problems associated with the operation of a VCSEL laser package operating at high frequencies (i.e. >1 Gb/s) were identified; possible solutions for typical driving configurations were then developed. The lessons learned from the analysis of the TO-46 and TO-56 cans were used to determine a rudimentary set of VCSEL package design guidelines. Finally, these guidelines were used to design and model a conceptual VCSEL laser package, dubbed optical package for advanced lasers (OPAL), capable of operation to data rates as high as 5 Gb/s. The modeling techniques used to match the TO-46 and the TO-56 time domain and frequency domain simulations to measurements were extrapolated to create a model of OPAL, and to evaluate it at high frequencies View full abstract»

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  • Excimer laser machining and metallization of vias in aluminum nitride

    Page(s): 241 - 246
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    Laser machining of ceramics is used extensively in the microelectronics industry for scribing and via hole drilling. Scribing involves laser ablation of a groove or row of holes that form perforation lines to separate a large substrate into individual circuits. Via machining is generally followed by a metallization step to create three-dimensional (3-D) interconnections in a multilayer circuit board. Aluminum nitride (AlN) is a desirable substrate material for high power, high frequency applications because of its high thermal conductivity and low thermal expansion coefficient than Al2O 3. In this paper, an excimer laser is used to machine high aspect ratio, straight walled via holes in aluminum nitride with or without a metallization layer deposited on the via walls. Via diameters range between 60 and 300 μm through substrates 635 μm thick. Through hole machining can cause damage to the back surface of the substrate, however, attachment of a second substrate or metal sheet will prevent damage. Ablation of the attached metal backing with subsequent redeposition on the via walls produces a metallized via with a resistance of less than 1 Ω per via. Single and multilayer via structures are described. Substrate damage at through hole exits results from shock wave propagation and reflection in the substrate. The attached backing material reduces reflection of the shock wave at the back surface of the substrate to prevent damage. Shock wave analysis, via cross sections, and resistance measurements are discussed View full abstract»

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  • Fast parameter extraction for multiconductor interconnects in multilayered dielectric media using mixture method of equivalent source and measured equation of invariance

    Page(s): 235 - 240
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    Measured equation of invariance (MEI) has been successfully used in many applications. It has been illustrated that the MEI is specially suitable for the decrease of computation time and computer memory space. However, for multiconductor interconnects in multilayered dielectric media, the Green's function is complex and the integrals of Sommerfeld type are time consuming. In this paper, equivalent source and measured equation of invariance (ES-MEI), a modification of the MEI, has been presented. Based on the equivalent principle, a reasonable illustration of the MEI can be obtained by ES-MEI. The node number is further decreased and the integrals of metron multiplied Green's function are avoided. It will be verified by several examples that the ES-MEI is very suitable for fast parameter extraction for multiconductor interconnects in multilayered dielectric media View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope