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Computers and Digital Techniques, IEE Proceedings -

Issue 4 • Date Jul 1997

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Displaying Results 1 - 8 of 8
  • Integrated concurrency control protocol for hard real-time database systems

    Publication Year: 1997 , Page(s): 214 - 218
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    Real-time transactions must meet their deadlines in hard real-time database systems (RTDBS). To preserve data integrity, hard RTDBS require concurrency control protocols to synchronise transactions to access shared data. Transaction blocking enforced by concurrency control protocols leads to priority inversion problems which violate the principle of priority-based scheduling and degrade system schedulability. Unfortunately, this blocking time can be indefinitely long, which is unacceptable in hard real-time applications. An integrated scheduling and concurrency control protocol is proposed that allows a high priority transaction to pre-empt an uncommitted lower priority transaction while preventing the lower priority transaction from being restarted even in the face of data conflicts. The new protocol alleviates priority inversion problems by allowing more transaction schedules than other protocols View full abstract»

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  • Analysis of delays in converting from a redundant representation

    Publication Year: 1997 , Page(s): 219 - 221
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    The use of a redundant number system allows many arithmetic operations to process digits sequentially, most significant digit first. Final conversion back to a standard binary representation can require time to propagate any carries. This paper analyses and reports on the delays encountered when this is done by an online algorithm, giving a good upper bound on the expected delay. The delay is approximately log,k for the kth digit in a representation with base r View full abstract»

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  • New algorithms for asynchronous communication

    Publication Year: 1997 , Page(s): 227 - 231
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    Concurrent processes are said to communicate asynchronously when there is no mutual timing interference resulting from their communication operations. This property can be achieved by mechanisms which use multiple shared memory locations (slots) to transfer data, and where access to these slots is co-ordinated by small shared control variables. Algorithms are known which allow a writing process to communicate asynchronously with a reading process through a four-slot mechanism with no mutual timing constraints. The paper gives new algorithms for a four-slot mechanism, and shows how these may be applied in a design. The new algorithms have an access-control strategy which is complementary to that used by the previously known algorithms View full abstract»

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  • Pollaczek-Khinchin formula for the M/G/1 queue in discrete time with vacations

    Publication Year: 1997 , Page(s): 222 - 226
    Cited by:  Papers (8)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    The continuous-time M/G/1 queue with vacations has been studied by many researchers. In the paper the authors report on an investigation of the discrete-time M/G/1 queue using Little's formula and conditional expectation. This direct approach can also be adopted to study the continuous-time case View full abstract»

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  • Improved control signal distribution for very wide VLSI data buses

    Publication Year: 1997 , Page(s): 209 - 213
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    A new technique for distributing electronic signals by way of a conducting path across large spatial distances with minimal temporal dispersion is presented. It provides for the delivery of a common signal to any number of different receivers located along the signal path, with near zero skew and little degradation of the signal's rise/fall transition involves the placement structure in parallel with, and appropriately strapped to, a conventional passive conductor. The concept is demonstrated in the paper, within the context of VLSI design, by a solution to the problem of distributing an on-chip control signal to the many lines of a physically very wide data bus View full abstract»

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  • V-fairness (t, n) secret sharing scheme

    Publication Year: 1997 , Page(s): 245 - 248
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    All secret sharing schemes proposed to date are not really fair on reconstructing a secret since there exists a probability ε, ε>0, such that a dishonest shareholder can obtain the secret while honest ones cannot. The paper proposes a V-fairness (t, n) secret sharing scheme, VFSS scheme, such that all shareholders have an equal probability of obtaining the secret without releasing their shadows simultaneously, even if V, V<t/2, shareholders are dishonest. Furthermore, the cheaters can easily be identified and they have no advantage over other participants during secret reconstruction View full abstract»

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  • Role model analysis of an asynchronous communication mechanism

    Publication Year: 1997 , Page(s): 232 - 240
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (852 KB)  

    The properties of asynchronous communication mechanisms which use multiple shared memory locations (slots) to transfer data, together with co-ordination of access to these slots by small shared control variables, can be examined by analysing the dynamically changing roles of the slots during asynchronous operation. The paper describes the application of the role modelling technique to a new form of four-slot mechanism, and analyses the correctness of the with respect to its coherence and properties. It is shown how other aspects, such as data sequencing and the failure modes of faulty implementation, can also be addressed View full abstract»

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  • Multireader and multiwriter asynchronous communication mechanisms

    Publication Year: 1997 , Page(s): 241 - 243
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    Mechanisms are known which allow asynchronous communication between a single writer and a single reader with no mutual timing constraints. Multireader and multiwriter forms can be constructed by simple replication of the one-reader-one-writer mechanisms. The paper gives a more integrated solution for a multireader mechanism which offers some economy over replication. The additional control logic required for a multiwriter solution is also derived. These solutions can be combined to give generalised multireader-multiwriter mechanisms View full abstract»

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