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Electron Devices, IEEE Transactions on

Issue 7 • Date Jul 1989

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Displaying Results 1 - 23 of 23
  • A new VDMOSFET structure with reduced reverse transfer capacitance

    Page(s): 1381 - 1386
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    A VDMOSFET structure with an additional p-region at the surface of the epitaxial layer is proposed. This structure realizes low reverse transfer capacitance without significantly degrading resistance. Reduction of the reverse transfer capacitance results in an improvement of the switching characteristics. The measured rise time is 49% and the fall time is 33% of the conventional VDMOSFET View full abstract»

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  • A low-noise gate structure for DMOS monolithic devices

    Page(s): 1393 - 1396
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    The effect of gate topology on the device noise figure of silicon double-diffused metal oxide semiconductor (DMOS) field-effect transistors is demonstrated and gate structures for DMOS devices with a noise figure approaching 1 dB at 500 MHz are presented. An analytical model for the output noise power and noise figure is given. The model is based on the assumptions that the device channel noise power spectrum is not correlated to the gate resistive noise and that the frequency is low enough so that the distributed effects of the gate structure are not significant. From this model, it is predicted that a large gate width is necessary for optimum low-noise performance View full abstract»

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  • A comparison of the GaAs MESFET and the AlGaAs/GaAs heterojunction bipolar transistor for power microwave amplification

    Page(s): 1274 - 1278
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    The study is normalized by constraining the devices to specific application: 1-W RF output power at 10 GHz. It is shown that the power gain and thermal resistance are higher and input impedances lower for the heterojunction bipolar transistor (HBT). Because of the higher thermal resistance, the operating temperature is significantly higher for the HBT, limiting the CW power output from the device. If the device area is increased to reduce the power density, then the input impedance (common emitter) will be proportionally reduced, making input matching much more difficult View full abstract»

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  • Interface contribution to GaAs/Ge heterojunction solar cell efficiency

    Page(s): 1238 - 1243
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    A solar cell formed by growing a p-on-n AlGaAs/GaAs heteroface homojunction on a thin Ge substrate is studied by investigating the contribution of the GaAs/Ge heterostructure to the solar-cell efficiency. The existence of interface states is required in the absence of a Ge p-n junction to produce the photovoltaic effect with an open-circuit voltage enhancement as experimentally observed. Dark current-voltage characteristics of the GaAs/Ge heterojunction are calculated when the carrier transport is by thermionic emission and tunneling mechanisms. The evaluations correctly explain the observed changes of efficiency, the decrease of fill factor, the increase of open-circuit voltage, and the insignificant change of short-circuit current as compared to a GaAs/GaAs solar cell. It the short-circuit current from the heterojunction is on the order of 25 mA/cm2, which is less than that of the p-n junction cell, the reduction of the solar cell efficiency is about 0.5-1.5% over a wide range of GaAs/Ge doping concentrations. Very few interface states tend to yield a diode-like dark I-V curve View full abstract»

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  • High-speed DCFL circuits with very shallow junction GaAs JFETs

    Page(s): 1387 - 1388
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    High-speed DCFL (direct-coupled FET logic) circuits implemented with advanced GaAs enhancement-mode J-FETs are discussed. A divide-by-four static frequency divider operates at up to 6 GHz with a power consumption of 20 mW/flip-flop. A high channel concentration of more than 1×1018 cm-3 together with a very shallow junction depth of less than 30 nm for the p+-gate results in a transconductance as high as 340 mS/mm at a gate length of 0.8 μm. Open-tube diffusion of Zn using diethylzinc and arsine makes it possible to control a very shallow p+-layer less than 10 nm thick. The propagation delay time, as measured with a ring oscillator, was 22 ps/gate with a power consumption of 0.42 mW/gate View full abstract»

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  • The superlinearity of the short-circuit current of low-resistivity-concentration solar cells

    Page(s): 1286 - 1294
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    It has been observed that Si solar cells respond superlinearly to irradiance while GaAs behaves linearly. Computer analysis of superlinear characteristics of short-circuit current with irradiances above 1 sun for low-resistivity Si concentrator cells has shown the importance of the base electric field in enhancing the collection efficiency of minority carriers generated in the base region. The effect of the base electric field can be incorporated into effective upstream and downstream diffusion lengths. The effective downstream diffusion length increases from 223 μm at one sun to near 1000 μm at 1000 suns in one case. Collection of minority carriers in the base alone due to the enhanced diffusion lengths is sufficient to explain the observed superlinearity View full abstract»

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  • Theoretical analysis of an Al0.15Ga0.85As/In 0.15Ga0.85As pseudomorphic HEMT using an ensemble Monte Carlo simulation

    Page(s): 1254 - 1263
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    The calculations presented include the full details of the two-dimensional electron gas, nonstationary transport effects, real-space transfer, and the effects of the two-dimensional electric field profile. As a test of the accuracy with which the calculations successfully model a real device, the calculated current-voltage characteristic is compared to the experimentally measured data for a comparable device. Excellent agreement is obtained between the theory and experiment. The effect of velocity overshoot and real-space transfer on the device performance is investigated as a function of gate and drain bias. It is found that at under certain gate-bias conditions, real-space transfer into both the AlGaAs and GaAs layers occurs, leading to an enhanced substrate leakage current as well as lowered overall speed of performance View full abstract»

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  • A new criterion for transient latchup analysis in bulk CMOS

    Page(s): 1336 - 1347
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    A criterion for transient latchup of p-n-p-n structures initiated by current pulses is described. Based on the circuit-orient model, the terminal currents and voltages of the transistors as a function of the pulsed triggering currents are characterized, and the charge storage within p-n-p-n structures is investigated. It is found that, to maintain the regeneration process, the change of charge stored in junction depletion capacitances of a p-n-p-n structure must be greater than a certain value independent of the triggering currents. Thus, the criterion is constructed in terms of the constant charge storage within a p-n-p-n structure. Applying the criterion, latchup immunity against pulsed triggering currents can be evaluated with respect to process and device parameters. Both SPICE simulations and experimental results confirm the validity of the proposed transient criterion. It is found that the large transit time of bipolar transistors and large well-substrate junction depletion capacitance lead to higher latchup immunity against pulsed triggering currents View full abstract»

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  • Integrated multi-biosensors based on an ion-sensitive field-effect transistor using photolithographic techniques

    Page(s): 1303 - 1310
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    Two kinds of multifunctional biosensors, one sensitive to glucose and triolein and the other to glucose and urea, have been constructed using semiconductor fabrication techniques. An integrated ISFET (ion-sensitive field-effect transistor) with three hydrogen-ion-sensitive FET elements on one chip was used as a transducer for the biosensor. A photolithographic technique with a water-soluble photocrosslinkable polymer made possible the deposition of patterned enzyme membranes (glucose oxidase, lipase, and urease membranes) and bovine serum albumin membrane around each gate surface of ISFET elements. The multibiosensor for measuring glucose and triolein concentrations determined both glucose concentrations up to 5 mM and triolein concentrations up to 3 mM simultaneously. The biosensor for glucose and urea has a detection range of 0.03 to 3 mM for glucose and 0.1 to 20 mM for urea. Some multibiosensors showed a cross-sensitivity problem due to enzyme contamination. An improved membrane fabrication method to prevent the enzyme contamination is described View full abstract»

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  • SATPOLY: a self-aligned tungsten on polysilicon process for CMOS VLSI applications

    Page(s): 1355 - 1361
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    The use of complementarily doped n+ and p+ polysilicon has been proposed for future generations of CMOS technology. The implementation of this technology requires low-resistance shunts both to reduce the overall resistance of the gate level interconnections and to short out the polysilicon p-n junctions. A process in which tungsten is chosen to provide the low-resistance shunts, with the necessary gate sidewall spacers formed before the selective deposition of tungsten, is described. A nonselective tungsten deposition process, originally developed explicitly for the implementation of direct tungsten gate MOS technology, is a key step in the formation of the spacers in the SATPOLY (self-aligned tungsten on polysilicon) process. The work function stability and the adhesion of the tungsten-polysilicon double-layer structure as a function of the polysilicon glue layer thickness have also been investigated View full abstract»

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  • Avalanche multiplication in a compact bipolar transistor model for circuit simulation

    Page(s): 1376 - 1380
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    A simple weak avalanche model valid in a wide range of voltages and currents, is presented. The proposed model is derived by using the base-collector depletion capacitance for predicting the avalanche current. The model needs only one additional transistor parameter; the extraction method and temperature dependence of this parameter are discussed. The decrease in avalanche current for high collector current densities may originate from internal device heating, a voltage drop in the epilayer, or mobile carriers in the depleted part. From experimental results it is concluded that, below a critical hot-carrier current, the decrease in avalanche current due to mobile carriers is negligible View full abstract»

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  • Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation

    Page(s): 1318 - 1335
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    It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (e.g., irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation. It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps. It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (e.g., for the case of hot-carrier degradations). All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given View full abstract»

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  • Subthreshold conduction in uniformly doped epitaxial GaAs MESFETs

    Page(s): 1264 - 1273
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    The channel gating function that determines the conducting cross section of the channel is calculated for the case of a uniformly doped epitaxial GaAs metal-semiconductor field-effect transistor (MESFET) by solution of the Poisson-Boltzmann equation for the n-layer/buffer (substrate) interface. This analysis improves on the depletion approximation by including the interaction between the depletion-edge transition regions of the gate and of the substrate space charge, thus providing a more accurate description of the carrier distribution in the channel for cases near to or into the pinchoff region. An analytical model is derived from the numerical results, and good agreement is found between this model and experimental devices View full abstract»

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  • Characterization of alloyed AuGe/Ni/Au ohmic contacts to n-doped GaAs by measurement of transfer length and under the contact sheet resistance

    Page(s): 1390 - 1393
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    The results of systematic measurements of transfer length L T and sheet resistance under the contact Rsk for alloyed AuGe/Ni/Au ohmic contacts to GaAs active layers prepared both by VPE (vapor-phase epitaxy) and by direct selective ion implantation are given. The end resistance measurement technique was used. Also reported are the more commonly measured specific interfacial resistance ρc and unit-width resistance rc. LT was relatively constant at 1.35 μm. A wide range for Rsk was observed, including values both higher and lower than the pre-alloyed value. It correlates with ρc and rc and demonstrates that variation in the GaAs/contact interface is the source of the commonly observed wide scatter in these parameters View full abstract»

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  • Substrate current model for submicrometer MOSFETs based on mean free path analysis

    Page(s): 1348 - 1354
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    The nonequilibrium effects of hot carriers are investigated to analyze avalanche generation for submicrometer MOSFET devices. A simple analytical expression for the impact ionization utilizing the mean free path concept is developed. It is incorporated into a conventional drift-diffusion equation solver (PISCES) to obtain the substrate current in submicrometer MOSFET devices. The transconductance for high drain bias and breakdown conditions are analyzed based on the proposed impact ionization model View full abstract»

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  • Simulation of circular silicon pressure sensors with a center boss for very low pressure measurement

    Page(s): 1295 - 1302
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    A characteristics simulation method of circular silicon-diaphragm piezoresistive pressure sensors was developed to obtain accurate sensors for very-low-pressure measurement. The anisotropic stress-strain relationship of a silicon single-crystal plate and the nonlinear characteristics of silicon piezoresistive gauges were considered. Nonlinear deflection and strain formulas of circular silicon diaphragm sensors with a center boss and sensors with a center boss and ribs were derived by taking the effects of the large deflection and the support stiffness of the diaphragms into account. Based on these considerations, the characteristics of the sensors were simulated. The simulated results show good agreement with the observed results and indicate that output voltage can be greatly increased while maintaining low nonlinearity even in the low-pressure range by narrowing the rib width and thinning the diaphragm thickness of sensors with a center boss and ribs. This is because the rib strain that produces output voltage is increased while maintaining small deflection by using this type of sensor View full abstract»

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  • A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation

    Page(s): 1370 - 1375
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    A super self-aligned process technology, SST-1B, which is an advanced version of the previously proposed SST-1A in high-speed Si bipolar LSIs is discussed. A selectively ion-implanted collector (SIC) process and bird's-beak-free isolation process are utilized. The SIC process is designed to improve shallow base-collector profiles in the intrinsic region. It reduces base width and intrinsic base resistance, and suppresses the base push-out effect (Kirk's effect) in high-current operations. The SIC profile is easily controlled by 150-200 keV phosphorous ion implantation at the base-collector junction. Using these processes, SST-1B has achieved a high cutoff frequency of 21.1 to 25.7 GHz and a fast switching delay of 20.5 ps/G for nonthreshold logic and 34.1 ps/G for emitter-coupled logic. SST-1B has potential applications to 50-ps/G logic LSIs and 10-GHz SSIs. Device simulation indicates that it is possible to achieve a cutoff frequency of 40-50 GHz in a future scaled-down Si bipolar transistor with a 40-nm base and graded collector View full abstract»

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  • Forward-bias conduction of Schottky diodes on polysilicon thin films

    Page(s): 1311 - 1317
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    An analysis of forward I-V characteristics for Al Schottky contacts to polycrystalline thin films is presented. Experimental results for lateral structures with various n- doping levels show the expected twofold exponential characteristics representing a transition from electrode-limited to bulk-limited conduction. At higher doping levels the bulk-limited characteristic is not a perfect exponential. The thermionic emission theory has been modified to include crystallite resistivity between grain boundaries and successfully matches experimental data View full abstract»

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  • An approach toward 25-percent efficient GaAs heteroface solar cells

    Page(s): 1230 - 1237
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    To approach one-sun 25% efficiency in GaAs solar cells, it is necessary to improve the basic understanding of internal loss mechanisms by a combination of characterization techniques and computer models. A methodology is developed to measure and evaluate minority-carrier transport properties such as lifetime and recombination velocity throughout the device structure in a 21.2% GaAs cell. It is found that this cell has a recombination velocity of 1.25×105 cm/s at the AlGaAs/GaAs interface and a base minority-carrier lifetime of 8 ns. Guidelines are provided to increase the efficiency of this cell to 24% with slightly increased surface passivation and base lifetime using effective recombination velocity and device modeling computer programs. Further device modeling is performed to show that efficiencies of 25% can be obtained using a modified heteroface structure with a moderate surface recombination and their relation to device design are fully understood View full abstract»

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  • An assessment of approximate nonstationary charge transport models used for GaAs device modeling

    Page(s): 1244 - 1253
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    A study of the utility of deterministic nonstationary models of charge transport in GaAs is presented. The models considered include energy and momentum conserving, energy conserving, and electron-temperature formulations. Predictions of the models are compared with results calculated using a more detailed Monte Carlo-based scattering-process-level simulation. The basis of the comparison is calculated trajectories in velocity-energy-field space for a range of time-dependent electric field forcing functions. All the nonstationary transport models considered are found to be in reasonable agreement with Monte Carlo results for all but the most extreme circumstances considered and to be greatly superior to the drift-diffusion approximation. Strengths, weaknesses, and applicability of individual models are discussed View full abstract»

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  • A BiCMOS process utilizing selective epitaxy for analog/digital applications

    Page(s): 1362 - 1369
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    A 2-μm BiCMOS process that has been designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar with an fT of 3.0 GHz, and a nonoptimized vertical p-n-p structure into a 2-μm CMOS process with poly-to-n+ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps, and with no changes to the critical process parameters that determine the performance of the MOS transistors. The circuit worthiness of the process is demonstrated by fabricating CMOS, vertical n-p-n RTL, and vertical p-n-p RTL ring oscillators, and demonstrating high yields for these circuits View full abstract»

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  • Generic parameterization of lifetime distributions

    Page(s): 1389 - 1390
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    In statistics and in reliability it is conventional to define a set of parameters for each cumulative distribution function. In contrast, here the use of generic parameters is considered. In particular, the standard deviation of the natural logarithm of the lifetime and the median of the lifetime are shown to be attractive generic parameters for semiconductor-device lifetimes. These two generic parameters are then evaluated for Weibull, exponential, lognormal, and nonparametric representations of the lifetime distribution View full abstract»

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  • The low-temperature anodization of silicon in a gaseous plasma

    Page(s): 1279 - 1285
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    A comprehensive investigation of the low-temperature anodization of silicon in RF and microwave oxygen plasmas is discussed. A comparison of the growth results and ion signals observed, using quadropole mass spectrometry, indicates a strong correlation between the growth rate and the presence of O- ions in the plasma. Characterization of parameters such as pressure, electrode spacing, and current density has allowed wafers up to 4-in. diameter to be anodized with good growth rates (0.3 μm/h) and excellent oxide uniformity, using low temperatures (⩽600°C), low input power densities (~59 W-cm-2), and low current densities (~7 mA-cm-2). Oxide properties such as etch rate and refractive index were found to be indistinguishable from thermally grown oxides. Optimization of anneals and the use of a halogen gas enables plasma oxides with high breakdown fields (10-11 MV/cm), an interface trap density of ~5×1010 cm-2-eV-1 at midgap, and a fixed oxide charge of 6×1010 cm-2 to be fabricated without resorting to high-temperature (⩾600°C) processing View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology