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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 3 • Sept. 1997

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Displaying Results 1 - 11 of 11
  • Fully coupled dynamic electro-thermal simulation

    Publication Year: 1997, Page(s):250 - 257
    Cited by:  Papers (54)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (921 KB)

    Fully coupled dynamic electro-thermal simulation on chip and circuit level is presented. Temperature dependent thermal conductivity of silicon is taken into account, thus solving the nonlinear heat diffusion equation. The numerical solution is carried out by using the industry-standard simulator SABER, therefore for electro-thermal simulations we are able to use the common electrical compact model... View full abstract»

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  • Electro-thermal and logi-thermal simulation of VLSI designs

    Publication Year: 1997, Page(s):258 - 269
    Cited by:  Papers (51)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1654 KB)

    Due to severe thermal problems of today's VLSI integrated circuits the need for reliable and quick thermal, electro-thermal and logi-thermal simulation tools is increasing, In this paper, we discuss the latest advances in the SISSI package (simulator for integrated structures by simultaneous iteration) which is a tool developed originally for analog VLSI design. The improvements include electro-th... View full abstract»

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  • CMOS sensors for on-line thermal monitoring of VLSI circuits

    Publication Year: 1997, Page(s):270 - 276
    Cited by:  Papers (58)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (746 KB)

    The paper presents appropriate sensors for the realization of the design principle of design for thermal testability (DfTT). After a short overview of the available CMOS temperature sensors, a new family of temperature sensors will be presented, developed by the authors especially for the purpose of thermal monitoring of VLSI chips. These sensors are characterized by the very low silicon area of a... View full abstract»

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  • Electro-thermal circuit simulation using simulator coupling

    Publication Year: 1997, Page(s):277 - 282
    Cited by:  Papers (67)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (641 KB)

    The paper presents a methodology for simulating the static and dynamic performance of integrated circuits in the presence of electro-thermal interactions on the integrated circuit die. The technique is based on the coupling of a finite element method (FEM) program with a circuit simulator. In contrast to other known simulator couplings a time step algorithm is used, Its implementation in simulatio... View full abstract»

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  • Realistic and efficient simulation of electro-thermal effects in VLSI circuits

    Publication Year: 1997, Page(s):283 - 289
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1048 KB)

    Needs for electro-thermal simulation of VLSI circuits, as opposed to both the system and device levels, are analyzed. A system capable of modeling these effects in a realistic and sufficiently accurate way that uses a reasonable amount of CPU resources is presented. An innovative solver is also proposed. The system is used to study the importance of some three dimensional (3-D) effects as well as ... View full abstract»

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  • Effects of simultaneous switching noise on the tapered buffer design

    Publication Year: 1997, Page(s):290 - 300
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (853 KB)

    Complementary metal-oxide-semiconductor (CMOS) output buffers, comprised of a series of tapered inverters, are used to drive large off-chip capacitances. The ratio of the size of transistors between two consecutive stages is the buffer taper factor. With higher frequency of operation and simultaneous switching of the output drivers, the parasitic inductance present at the pin-pad-package interface... View full abstract»

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  • CMOS current steering logic for low-voltage mixed-signal integrated circuits

    Publication Year: 1997, Page(s):301 - 308
    Cited by:  Papers (43)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of /spl Delta/V/sub logic//spl ap/V/sub dd/, a CSL gate swings only /spl Delta/V/sub logic//spl ap/V/sub T/+0.25 V because the constant current supplied by the PMOS loa... View full abstract»

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  • Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits

    Publication Year: 1997, Page(s):309 - 319
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1081 KB)

    This paper describes a new procedure to estimate the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical approaches to take advantage of their time-efficiency over conventional event-driven simulation tools. For this study, combinational circuits driven by discrete-time logic signals are considered. By focusing on a specific class... View full abstract»

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  • VLSI hardware for example-based learning

    Publication Year: 1997, Page(s):320 - 328
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1396 KB)

    Example-based learning, as performed by neural networks and other approximation and classification techniques, is both computationally intensive and I/O intensive, typically Involving the optimization of hundreds or thousands of parameters during repeated network evaluations over a database of example vectors. Although there Is currently no dominant approach or technique among the various neural n... View full abstract»

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  • A reconfigurable VLSI coprocessing system for the block matching algorithm

    Publication Year: 1997, Page(s):329 - 337
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1162 KB)

    Several VLSI architectures for the full-search block matching algorithm have been proposed in recent years due to its computation and I/O-intensive nature and its importance in various computer vision and image processing applications. This paper presents a new coarse grained reconfigurable coprocessor which is suitable for integration with general purpose microprocessors. The 180000 transistor cu... View full abstract»

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  • Design, analysis, and evaluation of concurrent checking sorting networks

    Publication Year: 1997, Page(s):338 - 343
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (610 KB)

    In this brief, we propose two new concurrent error-detection (CED) schemes for a class of sorting networks, e.g., odd-even transposition, bitonic, and perfect shuffle sorting networks. A probabilistic method is developed to analyze the fault coverage, and the hardware overhead is evaluated. We first propose a CED scheme by which all errors caused by single faults in a concurrent checking sorting n... View full abstract»

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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu