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Computers, IEEE Transactions on

Issue 3 • Date Mar 1988

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Displaying Results 1 - 17 of 17
  • A multiple-access pipeline architecture for digital signal processing

    Publication Year: 1988 , Page(s): 283 - 290
    Cited by:  Papers (5)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (708 KB)  

    The design of a special-purpose CMOS processor for digital signal processing is described. A high degree of processing concurrency is achieved through the use of two modified pipelined architectures in parallel. Each pipeline section is connected to a bus for maximum flexibility in accessing any stage in the pipeline. Each pipeline section can be dynamically configured under microprogram control t... View full abstract»

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  • The design of TSC error C/D circuits for SEC/DED codes

    Publication Year: 1988 , Page(s): 258 - 265
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (644 KB)  

    A design technique for totally self-checking (TSC) error correcting/detection (C/D) circuits of single error correcting, double error detection (SEC/DED) codes is described. The structure of these circuits achieves concurrent fault detection and location under normal input conditions. A separate internal fault indication is provided. This improves the reliability, maintainability, and availability... View full abstract»

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  • Random pattern testability of delay faults

    Publication Year: 1988 , Page(s): 291 - 300
    Cited by:  Papers (91)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (772 KB)  

    In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. Here, the capability of random patterns to detect slow paths in combinational logic is analyzed. Formulas that rela... View full abstract»

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  • The generation of a class of multipliers: synthesizing highly parallel algorithms in VLSI

    Publication Year: 1988 , Page(s): 329 - 338
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (768 KB)  

    A synthesis method for designing highly parallel algorithms in VLSI is presented. To illustrate the method, the familiar long multiplication algorithm for binary numbers is used. This algorithm is specified in the language Crystal, a very-high-level language for parallel processing. A total of 18 designs are derived from this specification. Each is optimal within its own class, which is characteri... View full abstract»

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  • The universality of a class of modified single-stage shuffle/exchange networks

    Publication Year: 1988 , Page(s): 348 - 352
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (420 KB)  

    A class of modified single-state shuffle/exchange (S/E) networks with reconfigurable connections is described. The capability of these modified networks to simulate every arbitrary permutation and other multistage S/E networks is studied. In particular, the upper bounds on simulating six multistage S/E networks are given. It is also shown that C.L. Wu and T.Y. Feng's (1981) modified single-stage S... View full abstract»

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  • An O(n+k) algorithm for ordered retrieval from an associative memory

    Publication Year: 1988 , Page(s): 368 - 371
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (424 KB)  

    The problem of retrieving an ordered list of k words that satisfy a given search condition from an associative memory of m words of n bits each is addressed. A fast ordered retrieval algorithm is proposed, along with a logic design for a cellular associative memory which mechanizes the algorithm. The algorithm is of time complexity O(n+k). By contrast, ... View full abstract»

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  • Decomposing banyan networks for performance analysis

    Publication Year: 1988 , Page(s): 371 - 376
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (516 KB)  

    A general form of input-destination distribution matrix increases state space exorbitantly, thus making any buffer at every state statistically different from another. Certain specific forms of input-destination distribution matrix to which many real-life cases may conform, are analyzed. The idea called decomposition is applied here for specific nonhomogeneous flows. State space is not allowed to ... View full abstract»

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  • Efficient modular design of TSC checkers for m-out-of-2m codes

    Publication Year: 1988 , Page(s): 301 - 309
    Cited by:  Papers (18)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (652 KB)  

    A design method of totally self-checking (TSC) m-out-of-2 m code checkers is presented. The design is composed basically of two full-adder/half-adder trees, each summing up the ones received on m input lines, and a k-variable two-pair two-rail code tree that compares the outputs of the two-adder tree. The only modules used are full-adders, half-adders, and two-v... View full abstract»

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  • Reliability analysis in distributed systems

    Publication Year: 1988 , Page(s): 352 - 358
    Cited by:  Papers (25)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (624 KB)  

    Reliability of a distributed processing system is an important design parameter that can be described in terms of the reliability of processing elements and communication links and also of the redundancy of programs and data files. The traditional terminal-pair reliability does not capture the redundancy of programs and files in a distributed system. Two reliability measures are introduced: distri... View full abstract»

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  • Storage management in virtual tree machines

    Publication Year: 1988 , Page(s): 321 - 328
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (780 KB)  

    Many parallel algorithms, particularly divide-and-conquer algorithms, may be structured as dynamic trees of tasks. In general, as parallelism increases, storage requirements also increase. A sequential program keeps storage requirements small by finishing one task (or procedure invocation) before going on to another, so that the entire task tree is never in existence at any one time. This correspo... View full abstract»

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  • Optimal design and sequential analysis of VLSI testing strategy

    Publication Year: 1988 , Page(s): 339 - 347
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (732 KB)  

    A method for determining the optimal testing period and measuring the production yield is discussed. With the increased complexity of VLSI circuits, testing has become more costly and time-consuming. The design of a testing strategy, which is specified by the testing period based on the coverage function of the testing algorithm, involves trading off the cost of testing and the penalty of passing ... View full abstract»

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  • A transition sequence generator for RAM fault detection

    Publication Year: 1988 , Page(s): 362 - 368
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (632 KB)  

    In verification of n-bit CMOS memories it is usual to supply a test address sequence having n2n transitions, one for each ordered pair of n-bit words which differ in a single bit. From an inductive definition of a sequence with these properties, a succession of algorithms yielding the logic circuit of a next-state generator for the sequence is develop... View full abstract»

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  • A single chip parallel multiplier by MOS technology

    Publication Year: 1988 , Page(s): 274 - 282
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (588 KB)  

    A parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication (a... View full abstract»

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  • Fault tolerance in multiprocessor systems without dedicated redundancy

    Publication Year: 1988 , Page(s): 358 - 362
    Cited by:  Papers (20)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (500 KB)  

    An algorithm called RAFT (recursive algorithm for fault tolerance) for achieving fault tolerance in multiprocessor systems is described. Through the use of a combination of dynamic space- and time- redundancy techniques, RAFT achieves fault tolerance in the presence of permanent as well as intermittent faults. Performance and reliability of multiprocessor systems using RAFT are determined as a fun... View full abstract»

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  • A pipeline design of a fast prime factor DFT on a finite field

    Publication Year: 1988 , Page(s): 266 - 273
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (588 KB)  

    A conventional prime factor discrete Fourier transform (DFT) algorithm of the Winograd type is used to realize a discrete Fourier-like transform on the finite field GF(qn ). A pipeline structure is used to implement this prime-factor DFT over GF(qn). This algorithm is developed to compute cyclic convolutions of complex numbers and to aid in... View full abstract»

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  • Further results on the performance evaluation of the split channel reservation multiple access protocol ATP-2 for local area networks

    Publication Year: 1988 , Page(s): 376 - 383
    Cited by:  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (528 KB)  

    The adaptive reservation protocol, referred to as ATP-2, uses two frequency separated subchannels, the request and information subchannels, for the request and information packets. The nature of the accessing algorithms for these two subchannels characterizes the overall ATP-2 protocol quality. Extended ATP-2 performance results are presented and a comparison is made between the ATP-2 and some oth... View full abstract»

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  • Tradeoffs between coupling small and large processors for transaction processing

    Publication Year: 1988 , Page(s): 310 - 320
    Cited by:  Papers (17)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1040 KB)  

    A methodology is developed to determine the number of processors needed to satisfy transaction throughput and response time requirements for processors of different MIPS (sizes). The minimum MIPS per processor required to satisfy response time and throughput constraints in a transaction processing complex of N coupled systems is also determined. For realistic overhead assumptions, despite... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org