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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 4 • Date Apr 1997

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Displaying Results 1 - 9 of 9
  • A high-speed 2-D topography simulator based on a pixel model

    Page(s): 386 - 397
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    A high-speed two-dimensional (2-D) topography simulator which operates in X-Windows has been developed. This program, named TIGER (Topography Image GEneration Routine), uses a newly developed pixel model, in which regions of the same material are depicted by pixels with the same value (i.e. the same color) and material boundaries are regarded as color boundaries. New cross-sectional profiles are sequentially created by drawing basic geometrical figures on a cross-sectional profile of a former process step. No complex operations are required for boundary line definition, such as loop removal. Realistic cross sections of an LSI with three interconnection layers and an SST transistor with a complex structure were created by this simulator. The total simulation time is only one or two minutes for all the processing steps of an LSI View full abstract»

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  • An evaluation of parallel simulated annealing strategies with application to standard cell placement

    Page(s): 398 - 410
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    Simulated annealing, a methodology for solving combinatorial optimization problems, is a very computationally expensive algorithm and, as such, numerous researchers have undertaken efforts to parallelize it. In this paper, we investigate three of these parallel simulated annealing strategies when applied to standard cell placement, specifically the TimberWolfSC placement tool. We have examined a parallel moves strategy, as well as two new approaches to parallel cell placement-multiple Markov chains and speculative computation. These algorithms have been implemented in ProperPLACE, our parallel cell placement application, as part of the ProperCAD II project. We have constructed ProperPLACE so that it is portable across a wide range of parallel architectures. Our parallel moves algorithm uses novel approaches to dynamic message sizing, message prioritization, and error control. We show that parallel moves and multiple Markov chains are effective approaches to parallel simulated annealing when applied to TimberWolfSC, yet speculative computation is wholly inadequate View full abstract»

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  • A smoothed boundary condition for reducing nonphysical field effects

    Page(s): 420 - 423
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    In this paper, we examine the problem associated with abruptly mixing boundary conditions in the context of a two dimensional semiconductor device simulator. Explicitly, this paper addresses the transition between an ohmic-type Dirichlet condition and a passivated Neumann boundary. In the traditional setting, the details of the transition between the two boundary types are not addressed and an abrupt transition is assumed. Subsequently, the calculated observables (most notably the potential) exhibit discontinuous derivatives near the surface at the point where the boundary type switches. This paper proposes an alternative condition which models the progression between the two boundary types through the use of a finite length, smoothed boundary whereby the numerical discontinuities are eliminated. The physical and mathematical basis for this smoothed boundary condition is discussed and examples of the technique's implementation given. It is found that the proposed boundary condition is numerically efficient and can be implemented in pre-existing device simulators with relative ease View full abstract»

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  • An efficient solution scheme for the spherical-harmonics expansion of the Boltzmann transport equation [MOS transistors]

    Page(s): 353 - 361
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    This paper investigates a number of numerical schemes applicable to the solution of the Boltzmann transport equation by means of a spherical-harmonics expansion (SHE). A new scheme is proposed that improves the solution at low energies, keeping the desired accuracy in the calculation of the mean quantities while saving a significant amount of CPU time. This is important in view of the applications of the method since the typical number of nodes to be used in the combined space-energy domain is in the range of 104-105 View full abstract»

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  • Minimal buffer insertion in clock trees with skew and slew rate constraints

    Page(s): 333 - 342
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    In this paper, we investigate the problem of computing a lower bound on the number of buffers required when given a maximum clock slew rate (or rise time) constraint and a predefined clock tree. Using generalized properties of published CMOS timing models, we formulate a novel nonlinear buffer insertion problem. Next, we derive an algorithm that bounds the capacitance for each buffer stage without sacrificing the generality of the timing models. With this capacitance bound we formulate a second linear buffer insertion problem, which we solve optimally in O(n) time. The basic formulation and algorithm are extended to include a skew upper bound constraint. Using these algorithms we propose further algorithmic extensions that allow area and phase delay tradeoffs. Our results are verified using SPICE3e2 simulations with MCNC MOSIS 2.0 μ models and parameters. Experiments with these test cases show that the buffer insertion algorithms proposed herein can be used effectively for designs with high clock speeds and small skews View full abstract»

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  • Performance-driven routing with multiple sources

    Page(s): 410 - 419
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    Existing routing problems for delay minimization consider the connection of a single source node to a number of sink nodes, with the objective of minimizing the delay from the source to all sinks, or a set of critical sinks. In this paper, we study the problem of routing nets with multiple sources, such as those found in signal busses. This new model assumes that each node in a net may be a source, a sink, or both. The objective is to optimize the routing topology to minimize the total weighted delay between all node pairs (of a subset of critical node pairs). We present a heuristic algorithm for the multiple-source performance driven routing tree problem based on efficient construction of minimum diameter minimum-cost Steiner trees. Experimental results on random nets with submicrometer CMOS IC and MCM technologies show an average of 12.6% and 21% reduction in the maximum interconnect delay, when compared with conventional minimum Steiner tree based topologies. Experimental results on multisource nets extracted from an Intel processor show as much as a 16.1% reduction in the maximum interconnect delay, when compared with conventional minimum Steiner tree based topologies View full abstract»

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  • A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation

    Page(s): 343 - 352
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    In this paper we introduce a new subthreshold conduction CAD model for simulation of VLSI subthreshold CMOS analog circuits and systems. This model explicitly formulates the back-gate bias effect and preserves the original advantages of the existing four-parameter model while reducing the fitting parameter number down to three. A transparent relationship between the fitting parameters and the process parameters has been derived, and its correlation with a recently widely used CAD model as well as with a well-known two-parameter model has been established. Our extensive measurement work on n-channel MOSFET's has highlighted the potential of the model in handling the variations in the subthreshold I-V characteristics at different back-gate biases arising from process variations. The mismatch analysis has further been successfully performed with emphasis on the reverse back-gate bias effect. In summary, the proposed model can serve as a promising alternative in the area of VLSI subthreshold CMOS analog circuit simulation View full abstract»

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  • Clock skew minimization during FPGA placement

    Page(s): 376 - 385
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    Unlike traditional ASIC technologies, the geometric structures of clock trees in a field-programmable gate array (FPGA) are usually fixed and cannot be changed for different circuit designs. Furthermore, the clock pins are connected to the clock trees via programmable switches. As a result, the load capacitances of a clock tree may be changed, depending on the utilization and distribution of logic modules in an FPGA. It is possible to minimize clock skew by carefully distributing the load capacitances or, equivalently, the logic modules used for the circuit design implementation. In this paper we present an algorithm for selecting logic modules used for circuit placement such that the clock skew is minimized. The algorithm can be applied to a variety of clock tree architectures, including those used in the major commercial FPGA's. The algorithm can also be extended to handle buffered clock trees and multiple clock trees Experimental results show that the algorithm can reduce clock skews significantly as compared with the traditional placement algorithms which do not consider clock skew minimization View full abstract»

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  • Verification of Tempura specification of sequential circuits

    Page(s): 362 - 375
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    Verifying a sequential circuit consists in proving that the given implementation of the circuit satisfies its specification. In the present work the input-output specification of the circuit, which is required to hold for the given implementation, is assumed to be available in the form of a Tempura program segment B. It captures the desired ongoing behavior of the circuit in terms of input-output relationships that are expected to hold at various time instants of the interval in question. The implementation is given as a formula WS of a first-order temporal equality theory, ℱ. Goal formulas of the form P ⊃ B have been introduced to capture the correctness property of the circuit in question. P is a formula of the equality theory ε contained in ℱ and encodes the initial state(s) of the circuit. A goal reduction paradigm has been used to formulate the proof calculus capturing the state transitions produced along the intervals. Formulas, called verification conditions (VC's), whose validity ensures the correctness of the circuit, are produced corresponding to the output equality statements in B. For finite state machines, VC's are formulas of propositional calculus and, therefore, require no temporal reasoning for their proofs. In fact, since binary decision diagram (BDD) representations are used throughout, their proofs become quite simple. The goal reduction rules proposed for iterative constructs also incorporate synthesis of invariant assertions over the states of the circuit. The proof of a nontrivial example has been presented. The paper concludes with a discussion on a broad overview of the building blocks of the verifier View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu