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IEEE Transactions on Computers

Issue 2 • Date Feb. 1988

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Displaying Results 1 - 18 of 18
  • Concurrent error detection using watchdog processors-a survey

    Publication Year: 1988, Page(s):160 - 174
    Cited by:  Papers (239)  |  Patents (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1523 KB)

    Concurrent system-level error detection techniques using a watchdog processor are surveyed. A watchdog processor is a small and simple coprocessor that detects errors by monitoring the behavior of a system. Like replication, it does not depend on any fault model for error detection. However, it requires less hardware than replication. It is shown that a large number of errors can be detected by mo... View full abstract»

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  • Exhaustive test pattern generation using cyclic codes

    Publication Year: 1988, Page(s):225 - 228
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The generation of exhaustive test patterns for VLSI circuits using linear feedback shift registers is described in terms of cyclic codes. Punctured cyclic codes are used to generate exhaustive test patterns of any length. A techniques for the generation of punctured cyclic codes is presented. A technique is also presented to reduce the size of test sets obtained from punctured cyclic codes View full abstract»

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  • A 20 bit logarithmic number system processor

    Publication Year: 1988, Page(s):190 - 200
    Cited by:  Papers (73)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA (pr... View full abstract»

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  • Embedding computation in one-dimensional automata by phase coding solitons

    Publication Year: 1988, Page(s):138 - 145
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    It is shown that some kind of meaningful computation can be embedded in very simple, microscopically homogeneous, one-dimensional automata, and in particular filter automata with a parity next-state rule. A systematic procedure is given for generating moving, periodic structures (particles). These particles exhibit soliton-like properties; that is, they often pass through one another with phase sh... View full abstract»

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  • A distributed resource management mechanism for a partitionable multiprocessor system

    Publication Year: 1988, Page(s):201 - 210
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (940 KB)

    A resource-management mechanism is presented for a multiprocessor system consisting of a pool of homogeneous processing elements interconnected by multistage networks. The mechanism aims at making effective use of hardware resources of the multiprocessor system in support of high-performance parallel computations. It can create many physically independent subsystems simultaneously without incurrin... View full abstract»

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  • A fast algorithm for optimum syndrome space compression

    Publication Year: 1988, Page(s):228 - 232
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A procedure for multiple-output combinational circuits is presented that yields the optimum space compressor while using counting for time compression. The procedure is intended for the built-in selftest environment where output response data compression is appropriate. Optimum is defined as the minimum number of error patterns missed by the combination of space and time compression. The procedure... View full abstract»

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  • On self-fault diagnosis of the distributed systems

    Publication Year: 1988, Page(s):248 - 251
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The problem of achieving fault diagnosis in a network of interconnected processing elements (called nodes) is considered. It is assumes that there is no central facility to control, coordinate or mediate among the processing elements. Every node can eventually determine the status of nodes and communication paths between them. A diagnostic algorithm for homogeneous systems (systems with only testi... View full abstract»

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  • Distributed sorting on local area networks

    Publication Year: 1988, Page(s):239 - 243
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    A straight-line-topology local area network (LAN) to which a number of nodes are connected either in series or in parallel is considered. A file F is arbitrarily partitioned among these sites. The problem studied is that of rearranging the records of the file such that the keys of records at lower-ranking sites are all smaller than those at higher-ranking sites. Lower bounds on the worst-... View full abstract»

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  • Your favorite parallel algorithms might not be as fast as you think

    Publication Year: 1988, Page(s):211 - 213
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    A problem that requires I inputs, K outputs and I computations is to be solved on a d-dimensional parallel processing machine (usually d⩽3). Finite transmission speed and other real-world conditions are assumed. It is proved that the time needed to solve the problem is tmax (I1d/, K... View full abstract»

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  • Analysis and design of nonequivalent multistage interconnection networks

    Publication Year: 1988, Page(s):232 - 237
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Nonequivalence of multistage interconnection networks is established by obtaining a reduced graph model and then partitioning it into several bipartite subgraphs. This is shown to transform nonequivalence to nonisomorphism, which can be easily determined by examining the intrinsic characteristics of undirected loops. A reverse process allows the design of nonequivalent networks View full abstract»

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  • Modular concurrency control and failure recovery

    Publication Year: 1988, Page(s):146 - 159
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1516 KB)

    An approach to concurrency control is presented; it is based on the decomposition of both the database and the individual transactions. This approach is a generalization of serializability theory in that the set of permissible transaction schedules contains all the serializable schedules. In addition to providing a higher degree of concurrency than that provided by serializability theory, this app... View full abstract»

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  • A reconfiguration algorithm for a double-loop token ring local area network

    Publication Year: 1988, Page(s):182 - 189
    Cited by:  Papers (15)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    A distributed algorithm to reconfigure a double-loop token-ring local area network following topological changes is presented. Each node, upon detection of a broken link, attempts to use another link, and when this is not possible it connects its input and output lines to form a loopback. The nodes communicate only with their neighbors and base their actions on the messages they receive and on the... View full abstract»

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  • Self-routing technique in perfect-shuffle networks using control tags

    Publication Year: 1988, Page(s):251 - 256
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    The self-routing technique using control tags on multiple-pass perfect-shuffle networks is generalized. In particular, they show that bit-permute-complement permutations can be realized and unscrambled in (2n-1) passes or less, where n=log2N , N being the number of terminals on either side. They also show that most of the frequently used permutations ... View full abstract»

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  • DPM: a measurement system for distributed programs

    Publication Year: 1988, Page(s):243 - 248
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    A framework for measuring the performance of distributed programs is presented. This framework includes a model of distributed programs, a description of the measurement principles and methods, and a guideline for implementing these ideas. The author describes a measurement system called the Distributed Programs Monitor (DPM), which he has constructed on the basis of these concepts. DPM has been i... View full abstract»

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  • Deductive fault simulation for sequential module circuits

    Publication Year: 1988, Page(s):237 - 239
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    A cost-effective method is presented for the deductive simulation of fault effects propagating through sequential functional modules that are described by the state-diagram representation of a Moore or Mealy automaton. The cornerstone of the method is a novel definition of the internal fault list of a sequential module. The method can be particularly useful for sequential modules when the state as... View full abstract»

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  • Performance modeling and measurements of real time multiprocessors with time-shared buses

    Publication Year: 1988, Page(s):214 - 224
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB)

    A closed queueing network model is constructed to address workload effects on computer performance for a highly reliable unibus multiprocessor used in real-time control. The model consists of multiserver nodes and a nonpreemptive priority queue. Use of this model requires partitioning the workload into task classes. The time-average steady-state solution of the queuing model directly produces usef... View full abstract»

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  • Modified Faddeeva algorithm for concurrent execution of linear algebraic operations

    Publication Year: 1988, Page(s):129 - 137
    Cited by:  Papers (17)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    An algorithm is described that provides an architectural framework for systematic execution of a wide class of linear algebraic operations using a single systolic array and simple data flow. The algorithm has been modified to use numerically stable Given's rotations and is therefore suited to any matrix problem of full rank. When the problem size exceeds that of the hardware array, it can be parti... View full abstract»

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  • Hybrid fault diagnosability with unreliable communication links

    Publication Year: 1988, Page(s):175 - 181
    Cited by:  Papers (11)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    Hybrid fault diagnosability in distributed multiprocessor systems is considered for the case in which, in addition to units being faulty, communication links among units can also be faulty. A hybrid fault situation is a (bounded) combination of hard and soft failing units. A novel hybrid fault diagnosability, denoted (t/ts -unit: σ-link)-diagnosability is introdu... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org