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IEEE Transactions on Computers

Issue 7 • Date Jul 1997

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Displaying Results 1 - 11 of 11
  • Compile-time scheduling of dynamic constructs in dataflow program graphs

    Publication Year: 1997, Page(s):768 - 778
    Cited by:  Papers (23)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Scheduling dataflow graphs onto processors consists of assigning actors to processors, ordering their execution within the processors, and specifying their firing time. While all scheduling decisions can be made at runtime, the overhead is excessive for most real systems. To reduce this overhead, compile-time decisions can be made for assigning and/or ordering actors on processors. Compile-time de... View full abstract»

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  • Concurrent asynchronous broadcast on the MetaNet

    Publication Year: 1997, Page(s):737 - 748
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The problem solved in this work is how multiple nodes in a network with an arbitrary topology can broadcast concurrently, in an asynchronous manner, to all other nodes. Asynchronous means that the nodes do not coordinate their broadcast, and, therefore, it is possible that all nodes will start to broadcast at the same time. Simultaneous broadcast by many nodes can cause traffic congestion, which c... View full abstract»

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  • High speed externally asynchronous/internally clocked systems

    Publication Year: 1997, Page(s):824 - 829
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    Externally asynchronous/internally clocked (EAIC) systems provide a means of reliable controller design and operation, and incorporate many advantages of both synchronous and fully asynchronous methodologies. The basic memory module of an internally-clocked system is the DFLOP the outputs of which are fully protected from metastability-generated anomalies. As a result, the only input constraint on... View full abstract»

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  • Test generation for multiple state-table faults in finite-state machines

    Publication Year: 1997, Page(s):783 - 794
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    A test generation procedure to detect multiple state-table faults in finite-state machines is proposed. The importance of multiple state-table faults and their advantages as test generation objectives to avoid the need for checking experiments are considered. The proposed procedure is based on a new method for implicit enumeration of large numbers of multiple faults by using incompletely specified... View full abstract»

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  • On slot allocation for time-constrained messages in dual-bus networks

    Publication Year: 1997, Page(s):756 - 767
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    Several access schemes have been suggested for dual-bus network topology, e.g., DQDB, Fasnet, CRMA, and Simple. It is therefore important to provide various services in this type of networks. This paper addresses the issue of guaranteeing the timely delivery of isochronous (real-time) messages with hard deadlines in slotted dual-bus networks. We propose a slot allocation scheme which can allocate ... View full abstract»

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  • Signed binary addition circuitry with inherent even parity outputs

    Publication Year: 1997, Page(s):811 - 816
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB)

    A signed binary (SE) addition circuit is presented that always produces an even parity representation of the sum word. The novelty of this design is that no extra check bits are generated or used. The redundancy inherent in a SE representation is further exploited to contain parity information View full abstract»

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  • On the correctness of inside-out routing algorithm

    Publication Year: 1997, Page(s):820 - 823
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB)

    Recently, a new routing algorithm called inside-out routing algorithm was proposed for routing an arbitrary permutation in the omega-based 2log2 N stage networks. This paper discusses the problems of the inside-out routing algorithm and shows that the suggested condition for proper routing in the omega-omega network is insufficient. An extended necessary and sufficient condition for pro... View full abstract»

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  • How to make a correct multiprocess program execute correctly on a multiprocessor

    Publication Year: 1997, Page(s):779 - 782
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    A multiprocess program executing on a modern multiprocessor must issue explicit commands to synchronize memory accesses. A method is proposed for deriving the necessary commands from a correctness proof of the underlying algorithm in a formalism based on temporal relations among operation executions View full abstract»

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  • All-to-all broadcasting in faulty hypercubes

    Publication Year: 1997, Page(s):749 - 755
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    A new fault-tolerant all-to-all broadcasting algorithm in an n-dimensional hypercube with up to [n/2] faulty links is given. An extension of this algorithm that can tolerate up to [n/2] faulty nodes is also described. These algorithms assume a multiport I/O model, meaning each node can send and receive messages from all its adjacent nodes simultaneously. The total time steps taken by the proposed ... View full abstract»

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  • Design of testable multipliers for fixed-width data paths

    Publication Year: 1997, Page(s):795 - 810
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades, and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths det... View full abstract»

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  • A self-testing nonincreasing order checker

    Publication Year: 1997, Page(s):817 - 820
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    In this paper, we design a new class of self-testing checkers, self-testing nonincreasing order checkers, for the first time. The self-testing nonincreasing order checker is a critical component to design concurrent checking VLSI sorters because it is capable of checking whether an arbitrary long sequence of numbers has been sorted, as well as testing itself during normal system operation View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org