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Computers, IEEE Transactions on

Issue 7 • Date Jul 1997

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Displaying Results 1 - 11 of 11
  • On the correctness of inside-out routing algorithm

    Publication Year: 1997 , Page(s): 820 - 823
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    Recently, a new routing algorithm called inside-out routing algorithm was proposed for routing an arbitrary permutation in the omega-based 2log2 N stage networks. This paper discusses the problems of the inside-out routing algorithm and shows that the suggested condition for proper routing in the omega-omega network is insufficient. An extended necessary and sufficient condition for proper routing in the omega-omega network is also suggested. However, it is unknown if any permutation can be successfully routed by a heuristic algorithm which follows the condition. Thus, the rearrangeability of the omega-omega network still remains an open problem View full abstract»

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  • On slot allocation for time-constrained messages in dual-bus networks

    Publication Year: 1997 , Page(s): 756 - 767
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    Several access schemes have been suggested for dual-bus network topology, e.g., DQDB, Fasnet, CRMA, and Simple. It is therefore important to provide various services in this type of networks. This paper addresses the issue of guaranteeing the timely delivery of isochronous (real-time) messages with hard deadlines in slotted dual-bus networks. We propose a slot allocation scheme which can allocate bandwidth for a set of isochronous message streams and provide deterministic deadline guarantees. The proposed slot allocation scheme is guaranteed to find a feasible slot allocation in the sense that all messages can be transmitted in a timely manner as long as the total message density is less than or equal to a certain threshold, where the total message density is defined as the summation of the ratio of maximum message size to message deadline over all streams. We also discuss the implementation details of this scheme, and compare our scheme with another bandwidth allocation scheme proposed by D. Saha et al. (1994) View full abstract»

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  • Test generation for multiple state-table faults in finite-state machines

    Publication Year: 1997 , Page(s): 783 - 794
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    A test generation procedure to detect multiple state-table faults in finite-state machines is proposed. The importance of multiple state-table faults and their advantages as test generation objectives to avoid the need for checking experiments are considered. The proposed procedure is based on a new method for implicit enumeration of large numbers of multiple faults by using incompletely specified faulty machines. Experimental results are presented to demonstrate the effectiveness of implicit fault enumeration in detecting large numbers of multiple faults and in guaranteeing detection of all the faults or all the faults up to a specific multiplicity View full abstract»

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  • Design of testable multipliers for fixed-width data paths

    Publication Year: 1997 , Page(s): 795 - 810
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades, and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths deteriorates substantially. In this paper, we propose new generic design schemes, based on residue number system arithmetic, to improve the overall testability of data paths. The approach uses, in the test mode, the truncated least significant bits of the product to increase the variety of patterns at the output of a multiplier. This, in turn, improves the fault detectability of multipliers, and consequently, have a remarkable impact on the overall testability of data paths. The proposed techniques can be incorporated with a minimal performance degradation and area overhead, and are independent of the multiplier architecture. Experimental analysis performed on four high-level synthesis benchmarks exhibits a significant improvement in the overall testability of the corresponding data-path implementations View full abstract»

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  • How to make a correct multiprocess program execute correctly on a multiprocessor

    Publication Year: 1997 , Page(s): 779 - 782
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB)  

    A multiprocess program executing on a modern multiprocessor must issue explicit commands to synchronize memory accesses. A method is proposed for deriving the necessary commands from a correctness proof of the underlying algorithm in a formalism based on temporal relations among operation executions View full abstract»

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  • Signed binary addition circuitry with inherent even parity outputs

    Publication Year: 1997 , Page(s): 811 - 816
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    A signed binary (SE) addition circuit is presented that always produces an even parity representation of the sum word. The novelty of this design is that no extra check bits are generated or used. The redundancy inherent in a SE representation is further exploited to contain parity information View full abstract»

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  • All-to-all broadcasting in faulty hypercubes

    Publication Year: 1997 , Page(s): 749 - 755
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    A new fault-tolerant all-to-all broadcasting algorithm in an n-dimensional hypercube with up to [n/2] faulty links is given. An extension of this algorithm that can tolerate up to [n/2] faulty nodes is also described. These algorithms assume a multiport I/O model, meaning each node can send and receive messages from all its adjacent nodes simultaneously. The total time steps taken by the proposed algorithms are near optimal, and they produce a factor of n less traffic than previously known algorithms View full abstract»

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  • A self-testing nonincreasing order checker

    Publication Year: 1997 , Page(s): 817 - 820
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (52 KB)  

    In this paper, we design a new class of self-testing checkers, self-testing nonincreasing order checkers, for the first time. The self-testing nonincreasing order checker is a critical component to design concurrent checking VLSI sorters because it is capable of checking whether an arbitrary long sequence of numbers has been sorted, as well as testing itself during normal system operation View full abstract»

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  • High speed externally asynchronous/internally clocked systems

    Publication Year: 1997 , Page(s): 824 - 829
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    Externally asynchronous/internally clocked (EAIC) systems provide a means of reliable controller design and operation, and incorporate many advantages of both synchronous and fully asynchronous methodologies. The basic memory module of an internally-clocked system is the DFLOP the outputs of which are fully protected from metastability-generated anomalies. As a result, the only input constraint on an internally clocked system is a minimum pulse width corresponding to the frequency of the internal clock. In an internally clocked system, a clock event is not generated until all DFLOPs have resolved into alogically defined state. Because the period of the internal clock depends only on propagation delay through the components of the system, the clock always operates at a maximum possible frequency. Several internally clocked systems, involving both static and dynamic logic, are analyzed by using PSPICE simulations and the results of some real time tests are reported for comparison purposes. The operation characteristics of the DFLOP are analyzed at the component level, and system level comparisons are made with previous work. With submicron CMOS designs using dynamic logic, the internal frequencies of EAIC systems are predicted to exceed 300 MHz with throughputs of less than four ns View full abstract»

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  • Concurrent asynchronous broadcast on the MetaNet

    Publication Year: 1997 , Page(s): 737 - 748
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    The problem solved in this work is how multiple nodes in a network with an arbitrary topology can broadcast concurrently, in an asynchronous manner, to all other nodes. Asynchronous means that the nodes do not coordinate their broadcast, and, therefore, it is possible that all nodes will start to broadcast at the same time. Simultaneous broadcast by many nodes can cause traffic congestion, which can result in a traffic loss. The main property of the broadcast algorithms presented in this work is that under any arbitrary broadcast pattern there will be no packet or cell loss due to internal traffic congestion. The routing mechanism used by the broadcast algorithm can be viewed as a variant of deflection routing, which means that a node makes on-line routing decisions based on the local flow of traffic (i.e., internal load conditions). Unlike other deflection techniques, the MetaNet routing is along a global sense of direction, which guarantees that packets will reach their destinations. Thus, we call this method convergence routing (previous deflection algorithms did not guarantee deterministic routing convergence, i.e., a cell/packet can be deflected indefinitely inside the network). As a result of the convergence property, the deflection routing used in this work is the only one with broadcast capability View full abstract»

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  • Compile-time scheduling of dynamic constructs in dataflow program graphs

    Publication Year: 1997 , Page(s): 768 - 778
    Cited by:  Papers (20)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    Scheduling dataflow graphs onto processors consists of assigning actors to processors, ordering their execution within the processors, and specifying their firing time. While all scheduling decisions can be made at runtime, the overhead is excessive for most real systems. To reduce this overhead, compile-time decisions can be made for assigning and/or ordering actors on processors. Compile-time decisions are based on known profiles available for each actor at compile time. The profile of an actor is the information necessary for scheduling, such as the execution time and the communication patterns. However, a dynamic construct within a macro actor, such as a conditional and a data-dependent iteration, makes the profile of the actor unpredictable at compile time. For those constructs, we propose to assume some profile at compile-time and define a cost to be minimized when deciding on the profile under the assumption that the runtime statistics are available at compile-time. Our decisions on the profiles of dynamic constructs are shown to be optimal under some bold assumptions, and expected to be near-optimal in most cases. The proposed scheduling technique has been implemented as one of the rapid prototyping facilities in Ptolemy. This paper presents the preliminary results on the performance with synthetic examples View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
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e-mail: pmo@computer.org