By Topic

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 3 • Date March 1997

Filter Results

Displaying Results 1 - 11 of 11
  • Crosstalk reduction for VLSI

    Page(s): 290 - 298
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    The performance of high-speed electronic systems is limited by interconnect-related failure modes such as coupled noise. We propose new techniques for alleviating the problems caused by coupling between signal lines on integrated circuits. We show that models used by previous work on coupled noise-constrained layout synthesis do not allow the use of several important degrees of freedom. These degrees of freedom include the ability to utilize dynamic noise margins rather than static noise margins, the dependence of coupled noise on drive strength, and the possibility of using overlaps to reduce susceptibility to noise. We derive an expression for the coupled noise integral and a bound for the peak coupled noise voltage which shows order of magnitude improvements in both accuracy and fidelity compared to the charge sharing model used in previous work. We use the new bounds to guide a greedy channel router, which manipulates exact adjacency information at every stage, allowing it to introduce jogs or doglegs when necessary for coupled noise reduction. Experimental results indicate that our algorithm compares favorably to previous work. The coupled noise is significantly reduced on benchmark instances. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure

    Page(s): 316 - 320
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    In this paper, we study the net assignment problem for a logic emulation system in the folded-Clos network interconnection, also referred to as the “partial crossbar interconnection structure”. Net assignment of two-terminal nets in this interconnection structure is guaranteed to be completed in polynomial time. However, net assignment of multiterminal nets becomes NP-complete. A previous paper by Butts et al. (1992) has proposed a simple heuristic to perform net assignment for multiterminal nets. Its results showed that it failed to complete routing of all nets for many cases. It is inadequate to have a net assignment algorithm which does not guarantee an exact solution, as the failure of interconnecting field programmable gate arrays (FPGA's) will result in the failure of mapping to the computing engine as a whole and will result in redoing the previous steps, e.g., partitioning of circuits. Therefore, we propose an exact algorithm to solve the net assignment problem. The exact algorithm will find a solution if one exists. However, the exact algorithm may take exponential time. Accordingly, a two-phase approach is taken in this paper. A time-efficient heuristic method is used first. The exact solver will be called only if the heuristic fails to deliver a solution View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Diagnostic fault simulation for synchronous sequential circuits

    Page(s): 299 - 308
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Logic optimization and equivalence checking by implication analysis

    Page(s): 266 - 281
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuck-at faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel minimization techniques based on Boolean division. Furthermore, effective heuristics are presented to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good” candidates for the minimization of the circuit. A main advantage of the proposed approach is that it operates directly on the structural netlist description of the circuit so that the technical consequences of the performed transformations can be evaluated in an easy way, permitting better control of the optimization process with respect to the specific goals of the designer. Therefore, the presented technique can serve as a basis for optimization techniques targeting nonconventional design goals. This paper only considers area minimization, and our experimental results show that the method presented is competitive with conventional technology-independent minimization techniques. For many benchmark circuits, our tool, the Hannover implication tool, based on learning (HANNIBAL) achieves the best minimization results published to date. Furthermore, the optimization approach presented is shown to be useful in formal verification View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pitfalls in delay fault testing

    Page(s): 321 - 329
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    In this paper, we examine delay models used in very large scale integration (VLSI) circuit testing. Our study is based on electrical-level simulation experiments. We present a comprehensive analysis of phenomena which significantly affect the actual delays but are not taken into account by the existing models used in testing. Because of these phenomena, for a given path in a circuit, tests commonly considered equivalent may result in different pass/fail decisions. Moreover, contrary to a common assumption, robust tests may fail to detect faults detectable by nonrobust tests. This may happen even in circuits in which all paths are robust testable. Our analysis questions the test quality offered by delay test procedures used so far View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer

    Page(s): 257 - 265
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    In the domain of combinational logic synthesis, logic minimization plays a vital role in determining the area and performance of the synthesized circuit. Logic minimization based on AND-OR decomposition of functions is a well studied area. However, minimization based on AND-XOR decomposition has received relatively lesser attention. Since many real-life combinational functions are XOR dominated, a logic minimizer producing efficient AND-XOR decomposition can lead to more efficient realization of such circuits. The computer-aided design tool KGPXORMIN presented in this paper is a multilevel AND-XOR minimizer which outperforms the scheme reported by Saul (1991) by 45.77% in the literal count metric. In general, most of the real-life and benchmark circuits are a combination of OR and XOR logic. In order to have area efficient realization, we need to have an efficient minimizer capable of judicious use of OR and XOR gates. An integrated tool KGPMIN has been developed which combines the AND-XOR minimizer KGPXORMIN and well-known AND-OR minimizer MISII. Depending on the measure of dominance of OR and XOR logic, it switches from one minimizer to the other during the decomposition phase. By judicious switching from one minimizer to the other, on the average, KGPMIN outperforms MISII by 64.08% in literal count and 45.16% in absolute gate area for the MCNC combinational logic benchmarks. It also outperforms KGPXORMIN by 17.46% in literal count and 34.32% in gate area. The number of levels of the circuits synthesized with KGPMIN can be found to be comparable with the figures arrived at from the application of MISII View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Rotation scheduling: a loop pipelining algorithm

    Page(s): 229 - 239
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    We consider the resource-constrained scheduling of loops with interiteration dependencies. A loop is modeled as a data flow graph (DFG), where edges are labeled with the number of iterations between dependencies. We design a novel and flexible technique, called rotation scheduling, for scheduling cyclic DFGs using loop pipelining. The rotation technique repeatedly transforms a schedule to a more compact schedule. We provide a theoretical basis for the operations based on retiming. We propose two heuristics to perform rotation scheduling and give experimental results showing that they have very good performance View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms

    Page(s): 309 - 315
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    Nonenumerative path-delay fault coverage estimation for combinational circuits estimates the fault coverage of a given test set without explicit enumeration of all paths in the circuit. In a recent nonenumerative method, it was proposed that a set C of lines be located in the circuit so that the set forms a cut and no lines in the set belong to the same path. Each line in the cut defines a subcircuit consisting of all paths that contain the line. Fault coverage may be obtained by working on all the subcircuits without double-counting path-delay faults. The main result of this paper is a polynomial time algorithm for finding a maximum cardinality set C. Besides its theoretical importance, our extensive experimental results on the ISCAS'85 benchmarks show that the larger the set C (and the number of subcircuits), the better the fault coverage estimation. More subcircuits may be generated only in a heuristic manner. It was proposed to consider two or more line-disjoint cuts Ci. We propose a technique where only one Ci must be a cut. This scheme is based on novel algorithms and results in more subcircuits than the previous one View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Specification and analysis of timing constraints for embedded systems

    Page(s): 240 - 256
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    Embedded systems consist of interacting hardware and software components that must deliver a specific functionality under constraints on relative timing of their actions. We describe operation delay and execution rate constraints, that are useful in the context of embedded systems. A delay constraint bounds the operation delay or specifies any of the thirteen possible constraints between the intervals of execution of a pair of operations. A rate constraint bounds the rate of execution of an operation and may be specified relative to the control flow in the system functionality. We present constraint propagation and analysis techniques to determine satisfaction of imposed constraints by a given system implementation. In contrast to previous purely analytical approaches on restricted models or statistical performance estimation based on runtime data, we present a static analysis in presence of conditionals and loops with the help of designer assists. The constraint analysis algorithms presented here have been implemented in a cosynthesis system, VULCAN, that allows the embedded system designer to interactively evaluate the effect of performance constraints on hardware-software implementation tradeoffs for a given functionality. We present examples to demonstrate the application and utility of the proposed techniques View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic verification of implementations of large circuits against HDL specifications

    Page(s): 217 - 228
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    This paper addresses the problem of verifying the correctness of gate-level implementations of large synchronous sequential circuits with respect to their higher level specifications in a hardware description language (HDL). The verification strategy is to verify containment of the finite state machine (FSM) represented by the HDL description in the gate-level FSM by computing pairs of compatible states. This formulation of the verification problem dissociates the verification process from the specification of initial states, whose encoding may be unknown or obscured during optimization and also enables verification of reset circuitry. To make verification of large circuits with merged data path and control tractable, the concept of strong containment is introduced. This is a conservative approach which exploits correspondence between data path-registers in the two descriptions without requiring any correspondence between the control units. We also present an important result and associated proof that computation of pairs of equivalent or compatible states can be achieved by considering subsets of the circuit outputs. Consequently, verification of circuits with large and diverse input-output sets, which was previously intractable due to lack of a single effective variable order for the binary decision diagrams (BDD's), is now feasible. Experimental results are presented for the verification of several industry level circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On optimal board-level routing for FPGA-based logic emulation

    Page(s): 282 - 289
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    In this paper, we consider a board-level routing problem which is applicable to field-programmable gate arrays (FPGA)-based logic emulation systems such as the Realizer System and the Enterprise Emulation System manufactured by Quickturn Design Systems. For the case where all nets are two-terminal nets, we present an O(n2)-time optimal algorithm where n is the number of nets. Our algorithm guarantees 100% routing completion if the number of interchip signal pins on each FPGA chip in the logic emulation system is less than or equal to the number of I/O pins on the chip. Our algorithm is based on iterative computation of Euler circuits in graphs. We also prove that the routing problem with multiterminal nets is NP-complete. Also we suggest one way to handle multiterminal nets using some additional resources View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu