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IEE Proceedings - Computers and Digital Techniques

Issue 2 • Date Mar 1997

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Displaying Results 1 - 12 of 12
  • Comparison of dynamic and static load-balancing strategies in heterogeneous distributed systems

    Publication Year: 1997, Page(s):100 - 106
    Cited by:  Papers (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (764 KB)

    Although dynamic load-balancing strategies have the potential of performing better than static strategies, they are inevitably more complex. Their complexity and the overheads involved may negate their benefits. A heterogeneous distributed system, with computers of different processing capability but the same functionality, has been examined for two dynamic and two static policies. The results sho... View full abstract»

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  • Alternative systolic array for non-square-root Cholesky decomposition

    Publication Year: 1997, Page(s):57 - 64
    Cited by:  Papers (4)  |  Patents (11)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (608 KB)

    A novel systolic array for the non-square-root LDLT method of Cholesky decomposition is presented. The systolic array is an alternative to that proposed by Brent and Luk (1983); displaying an improvement in efficiency and a lower hardware cost, arising from a reduction in the number of multipliers required. An application for the array is in real-time digital signal processing hardware ... View full abstract»

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  • Systematic design of key establishment protocols based on one-way functions

    Publication Year: 1997, Page(s):93 - 99
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (784 KB)

    Several existing one-way function based key exchange protocols are methodically analysed. The analyses provide valuable insight into the working of the protocols and reveal security weaknesses in some of the protocols. Alternative protocols are devised that cannot only be shown to be secure, but also are simple and elegant when compared with the existing protocols View full abstract»

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  • Distributed algorithms for mobile hosts

    Publication Year: 1997, Page(s):49 - 56
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (724 KB)

    In a mobile environment the physical movement of hosts causes changes in the physical topology of the network with time. Therefore, the direct execution of the existing distributed algorithms in a mobile environment renders them inefficient. Distributed algorithms are therefore modified by assigning proxies, which are static hosts in the network, to each of the mobile hosts. Proxies have been used... View full abstract»

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  • Planar constrained terminals over-the-cell router

    Publication Year: 1997, Page(s):121 - 126
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (636 KB)

    The authors present a new routing model for over-the-cell channel routing. A graph theoretical algorithm is then proposed to solve the new problem. The algorithm has a complexity of O(nk2), where n is the number of nets and k is the number of columns in the channel. It achieved a routing area reduction of 71.5% for the PRIMARY 1 benchmark example from MCNC, using three-layer over-the-ce... View full abstract»

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  • Multilevel logic synthesis technique for efficient verification testing

    Publication Year: 1997, Page(s):83 - 91
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (844 KB)

    To improve the verification testability of multilevel circuits, a multilevel logic synthesis technique, called VETERAN, for verification testability has been developed. The main steps in VETERAN are first, the determination of the minimum sets of input variables (referred to as `minimum variable supports') for each output function. Secondly, an efficient verification testing scheme is derived from... View full abstract»

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  • Generic systolic array for genetic algorithms

    Publication Year: 1997, Page(s):107 - 119
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1392 KB)

    The authors present a systolic design for a simple GA mechanism which provides high throughput and unidirectional pipelining by exploiting the inherent parallelism in the genetic operators. The design computes in O(N+G) time steps using O(N2) cells where N is the population size and G is the chromosome length. The area of the device is independent of the chromosome length and so can be ... View full abstract»

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  • Design of a clock synchronisation sub-system for parallel embedded systems

    Publication Year: 1997, Page(s):65 - 73
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1012 KB)

    Software tools are being developed to support a design methodology specific to parallel real-time continuous-dataflow embedded systems. The authors describe the design of a global clock sub-system which is an essential component of an event trace tool. A new amalgam of algorithms is proposed which attends to the trade-off between clock accuracy and the need to restrict disturbance of the applicati... View full abstract»

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  • VHDL generation from hierarchical Petri net specifications of parallel controllers

    Publication Year: 1997, Page(s):127 - 137
    Cited by:  Papers (25)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1004 KB)

    Parallel controllers can be best specified using a description with a formal support to validate structural and dynamic properties. Petri nets (PN) can provide an adequate means to model and to animate parallel systems based on the control and data path approach, in a hierarchically structured way. A set of tools was developed to allow formal validation of parallel controllers, based on hierarchic... View full abstract»

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  • Efficient scheduling of behavioural descriptions in high-level synthesis

    Publication Year: 1997, Page(s):75 - 82
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1108 KB)

    A new heuristic scheduling algorithm for time constrained datapath synthesis is described. The algorithm is based on the distribution graph concept where a least mean square error function is used to schedule operations in sequence, resulting in a computationally efficient solution with the capability of including other high-level synthesis features such as register cost without significant increa... View full abstract»

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  • HDL-specific source level behavioural optimisation

    Publication Year: 1997, Page(s):138 - 144
    Cited by:  Papers (1)  |  Patents (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (636 KB)

    Optimisation is a key facet of the behavioural synthesis problem. The process may be carried out at different levels in the processing, usually at the source or datapath levels, or both. In a previous paper, the authors reported a source level VHDL optimiser which applies optimisation techniques derived from conventional sequential and parallel programming languages. This process produces structur... View full abstract»

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  • Conference key distribution system with user anonymity based on algebraic approach

    Publication Year: 1997, Page(s):145 - 148
    Cited by:  Papers (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (388 KB)

    Most previously proposed conference key distribution systems (CKDSs) have been performed through modular exponentiation, which makes them inefficient in practical usage, especially in the case that the attending principals of the conference have less computing power. Extended from the Diffie-Hellman key distributed system (KDS), we propose an efficient CKDS with user anonymity based on the algebra... View full abstract»

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