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IEE Proceedings - Computers and Digital Techniques

Issue 1 • Date Jan 1997

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Displaying Results 1 - 9 of 9
  • Global linear complexity analysis of filter keystream generators

    Publication Year: 1997, Page(s):33 - 38
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (544 KB)

    An efficient algorithm for computing lower bounds on the global linear complexity of nonlinearly filtered PN-sequences is presented. The technique here developed is based exclusively on the realisation of bitwise logic operations, which makes it appropriate for both software simulation and hardware implementation. The algorithm can be applied to any arbitrary nonlinear function with a unique term ... View full abstract»

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  • Low test-application time method for EEPLA testing

    Publication Year: 1997, Page(s):39 - 42
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (344 KB)

    An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Usin... View full abstract»

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  • Dual basis systolic multipliers for GF(2m)

    Publication Year: 1997, Page(s):43 - 46
    Cited by:  Papers (12)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (332 KB)

    Two systolic multipliers for GF(2m) are presented, one bit-serial and one bit-parallel. Both multipliers are hardware efficient and support pipelining. Both architectures are highly regular, require only local communication lines and have longest delay paths independent of m. Consequently these multipliers can be clocked at high speeds and are suitable for VLSI implementation. The desig... View full abstract»

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  • Source level optimisation of VHDL for behavioural synthesis

    Publication Year: 1997, Page(s):1 - 6
    Cited by:  Papers (1)  |  Patents (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (596 KB)

    Optimisation in high level behavioural synthesis is usually performed by applying transforms to the datapath and control graphs. An alternative approach, however, is to apply transforms at a higher level in the process, specifically directly to the behavioural source description. This technique is analogous to the way in which the source code of a conventional sequential programming language may b... View full abstract»

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  • Enhancing the security of El Gamal's signature scheme

    Publication Year: 1997, Page(s):47 - 48
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (152 KB)

    The use of more than one hard problem in the design of cryptographic protocols to enhance security has already been proposed. To this end, a way to embed the discrete logarithm problem as well as the factorisation problem in the signing process in the original El Gamal signature scheme has been described. It is shown that the described modification does not enhance the security of the original sch... View full abstract»

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  • Design and application of Parsim-a message-passing computer simulator

    Publication Year: 1997, Page(s):7 - 14
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (736 KB)

    Currently many interconnection networks and parallel algorithms exist for message-passing computers. Users of these machines wish to determine which message-passing computer is best for a given job, and how it will scale with the number of processors and algorithm size. The paper describes a general purpose simulator for message-passing multiprocessors (Parsim), which facilitates system modelling.... View full abstract»

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  • Optimal fault-tolerant design approach for VLSI array processors

    Publication Year: 1997, Page(s):15 - 21
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (604 KB)

    A systematic approach for designing a fault-tolerant systolic array using space and/or time redundancy is proposed, The approach is based on a fault-tolerant mapping theory which relates space-time mapping and concurrent error detection techniques. By this design approach, the resulting systolic array is fault tolerant and achieves the optimal space-time product. In addition, it has the capability... View full abstract»

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  • Efficient cheater identification method for threshold schemes

    Publication Year: 1997, Page(s):23 - 27
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (448 KB)

    Cheating detection is a very important issue for threshold schemes. An efficient and simple cheating detection and cheater identification method is proposed in this paper. The attack of the proposed method is as difficult as factoring the product of two large prime numbers, the intractability of which forms the basis for RSA. The proposed method is more efficient than Wu et al.'s and Hwang et al.'... View full abstract»

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  • Logic for verifying public-key cryptographic protocols

    Publication Year: 1997, Page(s):28 - 32
    Cited by:  Papers (8)  |  Patents (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (540 KB)

    A number of techniques based on logic theories have recently been developed to provide formal verification of security protocols. Many of these are based on logics of belief, which are considered useful in evaluating the trust which may be placed in a security protocol. Other techniques are based on logics of knowledge, which are suitable for proving protocol security. A new logic is proposed in t... View full abstract»

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