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Computers and Digital Techniques, IEE Proceedings E

Issue 4 • Date Jul 1989

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Displaying Results 1 - 14 of 14
  • Error propagation property and application in cryptography

    Page(s): 262 - 270
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    The paper deals with the measurement of error propagation properties of Boolean functions and permutations. The author considers two such measurements. The first describes the output response when a single-bit input change occurs. The second characterises the output for double-bit changes. Those two measurements (in the paper termed indicators) have been applied to the permutations used in the DES cryptosystem and to the permutations generated by exponentiation. View full abstract»

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  • Object-background segmentation using new definitions of entropy

    Page(s): 284 - 295
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (980 KB)  

    The definition of Shannon's entropy in the context of information theory is critically examined and some of its applications to image processing problems are reviewed. A new definition of classical entropy based on the exponential behaviour of information-gain is proposed along with its justification. Its properties also include those of Shannon's entropy. The concept is then extended to fuzzy sets for defining a non-probabilistic entropy and to grey tone image for defining its global, local and conditional entropy. Based on those definitions, three algorithms are developed for image segmentation. The superiority of these algorithms is experimentally demonstrated for a set of images having various types of histogram. View full abstract»

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  • TOMP project

    Page(s): 225 - 233
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    The main objective of the TOMP (Torino multiprocessor) project was the development of a frame under which a wide variety of multiple processor systems could be sized up, designed, and built. The frame was not conceived for a specific purpose, the basic goal being to cover a wide area of applications, where the key parameters were the relevance of the distribution of the functions, and the computational needs required by real-time applications. The paper presents the methodologies used throughout the project, describing the development and the use of description and performance evaluation techniques, the choices at the architectural level, the design of a high-performance backplane bus, the basic software developed to make the hardware operational, and the results of some experiments on parallel programming. View full abstract»

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  • On designing robust testable CMOS combinational circuits

    Page(s): 329 - 338
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (856 KB)  

    The potential invalidation of two-pattern tests for detecting stuck-open faults in CMOS combinational circuits has been studied from a functional point of view. Two methods of testable realisations avoiding the problem are presented. A new type of two-level testable realisation is proposed in which both stuck-open and stuck-short faults can be detected. In both the methods, valid test patterns are applied at the inputs and the logic responses are observed at the output. Finally, multilevel realisations of combinational functions have been considered in which all stuck-short faults are three-pattern testable and all stuck-open faults are two-pattern testable. View full abstract»

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  • Efficiency of state assignment methods for PLA-based sequential circuits

    Page(s): 247 - 253
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    The implementation of finite sequential machines by using a programmable array logic to synthesise their combinational part is considered. A critical view of the efficiency of existing methods to carry out the state assignment of these machines is given, and it is shown that the authors can derive a bound on the number of state variables beyond which even an arbitrary coding usually leads to better results in terms of area occupation. It is suggested in the paper that this bound can still be found when more refined area estimates are used. View full abstract»

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  • Efficient realisation of discrete Fourier transforms using the recursive discrete Hartley transform

    Page(s): 254 - 261
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    The authors present the results of their study using a recursive discrete Hartley transform technique to compute discrete Fourier transforms. They also introduce an improved in-place and in-order prime-factor mapping to effectively realise composite-length DFTs. In using these new techniques, the speed of computation is comparable to that of the Winograd Fourier transform algorithm (WFTA), whereas the program size of the present approach is much smaller than that of the WFTA. This approach is most suitable for the cases where there are restrictions on program lengths. View full abstract»

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  • Binary decision graph reduction

    Page(s): 277 - 283
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    An estimator of the complexity of a binary decision graph is introduced. Based on this, an essentially tabular method of binary decision graph minimisation is presented. The method covers multiple-valued, incompletely specified Boolean systems. The method is well-structured and easily programmable. View full abstract»

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  • Syntactic translation and logic synthesis in Gatemap

    Page(s): 321 - 328
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    Gatemap is a logic synthesis system for digital integrated-circuit design, which automatically generates gate-level circuit implementations from behavioural Ella descriptions. These behavioural descriptions may contain a variety of arithmetic, relational and logical operators expressed using the Ella hardware design and description language. A process of syntactic translation is used to convert this input into minimised Boolean equations. Various logic synthesis techniques are then used to implement these equations using technology-specific logic gates. The final output is a variety of netlists for input to gate-level simulators and layout tools. Currently, two CMOS gate-array and one CMOS cell-based process technologies are supported, though further CMOS technologies could be addressed via the provision of the appropriate libraries. View full abstract»

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  • New array processor architectures for two-dimensional FIR digital filters

    Page(s): 234 - 238
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    A new array processor architecture for two-dimensional (2D) FIR digital filters is developed. The processor has two processing rates for processing 2D signals in two directions. It processes the input signal using a row-by-row scheme. Owing to its high speed (about 30 images per second), it can be used for real-time image processing. View full abstract»

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  • A low-cost text retrieval machine

    Page(s): 271 - 276
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    The paper introduces the design and implementation of a text retrieval hardware unit. After surveying a number of hardware text retrieval packages, it proposes a linguistic approach, in which the retrieval is treated as a regular expression which can be recognised by a finite state machine. The design of a finite state machine interpreter is given, and the problems of compiling a regular expression for this interpreter discussed. The algorithm for the compilation is given. Performance figures for the hardware, when connected to real systems, are given. View full abstract»

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  • Influence of guiding testability measure on number of backtracks of ATPG program

    Page(s): 316 - 320
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    A major problem, in accelerating an algorithm for test generation, is how to reduce the number of backtracks. The paper considers different measures of controllability and observability, and compares the number of backtracks obtained on large combinational circuits. The paper proposes a new controllability measure which is, on average, more efficient than the others. View full abstract»

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  • Charge-coupled device implementation of multivalued logic systems

    Page(s): 306 - 315
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    A survey of recent developments in the implementation of multivalued logic circuits using charge-coupled device technology is presented. A set of basic logic gate structures which is suitable for synthesis of both binary and multivalued functions is defined. Techniques for synthesis of one- and two-variable functions is considered in detail. A special case of threshold functions is emphasised. Finally, realisation of multivalued functions in terms of programmable logic arrays is described. View full abstract»

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  • Maximum pulse-position and counting errors of binary rate multipliers

    Page(s): 296 - 305
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    The paper examines systematically the error properties of binary rate multipliers (BRMs). Simple close-form expressions for the maximum pulse-position and counting errors are given for a number of timing variants. It is seen from the paper that the so far reported estimates of the errors, valid for a certain timing variant, are too optimistic in general. A brief discussion of the effect on the errors of a frequency divider applied to the output of the BRM is also provided. View full abstract»

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  • Block diagonal structure in discrete transforms

    Page(s): 239 - 246
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    The author investigates and summarises some of the computational tasks of discrete transforms in which block diagonal structure plays a dominant role. Walsh-Hadamard transform (WHT) based algorithm designs for various well known discrete transforms are presented; it can be proved that, owing to their block diagonal structure, the WHT based discrete transforms are more efficient than those of the conventional radix-r algorithms for transforms of length N View full abstract»

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