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IEEE Transactions on Computers

Issue 9 • Sept. 1989

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Displaying Results 1 - 17 of 17
  • Incremental computation of squares and sums of squares

    Publication Year: 1989, Page(s):1325 - 1328
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (205 KB)

    An incremental algorithm for computation of sums of squares is presented that is suitable for both most-significant-bit- (MSB-)first and least-significant-bit- (LSB-)first bit-sequential operation. By exploiting symmetry properties of numerical values and evaluation times in the bit-product matrix, it is shown how incremental multipliers can be converted to perform squaring at reduced hardware cos... View full abstract»

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  • Comments, on "A signed bit-sequential multiplier" by T. Rhyne and N.R. Strader II

    Publication Year: 1989, Page(s):1328 - 1330
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB)

    With reference to the above mentioned paper (see ibid., vol.C-35, p.896-901 (1986)), it is stated that the authors' introduction, in which they claim that the references all deal with algorithms for processing unsigned operands, is erroneous. One of their references most certainly does not deal with unsigned operands, as a two's complement number system is one of the module interfacing conventions... View full abstract»

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  • Comments, on "Design and evaluation of a fault-tolerant multiprocessor using hardware recovery blocks" by Y.-H. Lee and K.G. Shin

    Publication Year: 1989, Page(s):1336 - 1337
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (218 KB)

    The author shows that formula (9) of the above mentioned paper (see ibid., vol.C-33, p.113-124, (1984)) is erroneous. A new solution is proposed, and its congruency is shown.<> View full abstract»

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  • Optimal search policies for searches with I/O bound tasks

    Publication Year: 1989, Page(s):1314 - 1320
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    Two models are presented for conducting simple searches under the assumption that the tasks within the search tree are complex and may be I/O bound. The objective is to achieve the minimum expected time to completion. The simpler model assumes that the search paths are disjoint. The optimal policy in the general case is to run the tasks with the highest ratio of success probability per cycle expen... View full abstract»

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  • AT2-optimal Galois field multiplier for VLSI

    Publication Year: 1989, Page(s):1333 - 1336
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    VLSI designs for Galois field multipliers, which are central in many encoding and decoding procedures for error-detecting and error-correcting codes, are presented. An AT2-optimal Galois-field multiplier based on AT 2-optimal integer multipliers for a synchronous VLSI model is exhibited. Galois field multiplication is done in two steps. First two polynomials... View full abstract»

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  • Utilizing multidimensional loop parallelism on large scale parallel processor systems

    Publication Year: 1989, Page(s):1285 - 1296
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB)

    Program parallelism and processor allocation issues for parallel processor systems are discussed. Optimal processor assignment algorithms are presented for simple and complex nested parallel loops. These processor assignment schemes can be used by the compiler to perform static processor allocation to multiply nested parallel loops. Speedup measurements for EISPACK and IEEE DSP subroutines that re... View full abstract»

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  • A design approach for self-diagnosis of fault-tolerant clock synchronization

    Publication Year: 1989, Page(s):1337 - 1341
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    A general design approach for self-diagnosis of faulty clocking modules in a fault-tolerant clock synchronization (FTCS) system is presented. The approach is based on a statistical testing method. The major advantages are better self-stability control and lower overhead. The design methodology includes a self-diagnosis algorithm to transform a partially self-stabilizing clocking system into a self... View full abstract»

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  • On the complexity of scheduling problems for parallel/pipelined machines

    Publication Year: 1989, Page(s):1308 - 1313
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    The problem of optimal scheduling of a job system for two dedicated processors is presented. A machine model with two functional units which can be either sequential or pipelined is considered. The complexity of optimal scheduling for a set of expressions on such machines is investigated. Some previous NP-completeness results are reviewed and several new ones are presented. For one restricted case... View full abstract»

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  • All-to-all broadcast by flooding in communications networks

    Publication Year: 1989, Page(s):1330 - 1333
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The author establishes the worst-case time complexity of all-to-all broadcast, which involves the simultaneous broadcast of messages from each node in a network to each other node, as with the dissemination of network status information for adaptive routing in ARPANET, by flooding. It it shown to be almost two times the optimum. This suboptimality of flooding results from the selection method perm... View full abstract»

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  • Simulation of a word recognition system on two parallel architectures

    Publication Year: 1989, Page(s):1269 - 1284
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1220 KB)

    The use of two parallel architectures, a single-instruction-stream, multiple-data-stream (SIMD) machine and a VLSI processor array, to implement an isolated word recognition system is examined. SIMD and VLSI processor array algorithms are written for each of the components of the recognition system. The component parallel algorithms are simulated along with two complete recognition systems, one co... View full abstract»

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  • Distributed algorithms for network recognition problems

    Publication Year: 1989, Page(s):1240 - 1248
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB)

    The problem of recognizing whether a given network is a tree, ring, star, complete graph, or bipartite graph is considered. Unified algorithms to recognize if the network is any one of the above are presented in each of three classes of algorithms-with centralized, decentralized, and noncentralized initiations. It is shown that the communication and time complexities of the centralized algorithm a... View full abstract»

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  • Systolic Gaussian elimination over GF(p) with partial pivoting

    Publication Year: 1989, Page(s):1321 - 1324
    Cited by:  Papers (15)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A systolic architecture is proposed for the triangularization by means of the Gaussian elimination algorithm of large dense n×n matrices over GF(p), where p is a prime number. The solution of large dense linear systems over GF(p) is the major computational step in various algorithms issuing from arithmetic number theory and computer algebra. The ... View full abstract»

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  • Reconfigurable multipipelines for vector supercomputers

    Publication Year: 1989, Page(s):1297 - 1307
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB)

    The problem of recovering multipipelines in the presence of faulty stages is addressed. The stages are assumed to be organized in rows and columns. The pipeline stages are alternated with reconfiguring circuitry which is used for bypassing the faulty stages. The pipelines are configured by programming the switches in a distributed manner using fault information available locally. The configuration... View full abstract»

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  • On serial-input multipliers for two's complement numbers

    Publication Year: 1989, Page(s):1341 - 1345
    Cited by:  Papers (17)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The author shows that a multiplier already proposed by T. Rhyne and N.R. Strader (see ibid., vol.C-35, p.896-901 (1986)) for unsigned numbers can be used for two's complement numbers as well, provided only that the content of the input registers is held constant, after the introduction of the operand's sign bits, for a number of clock periods equal to the operand's length. The result is derived by... View full abstract»

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  • Optimum broadcasting and personalized communication in hypercubes

    Publication Year: 1989, Page(s):1249 - 1268
    Cited by:  Papers (473)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1736 KB)

    Four different communication problems are addressed in Boolean n-cube configured multiprocessors: (1) one-to-all broadcasting: distribution of common data from a single source to all other nodes; (2) one-to-all personalized communication: a single node sending unique data to all other nodes; (3) all-to-all broadcasting: distribution of common data from each node to all other nodes; and (4... View full abstract»

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  • Polymorphic-torus network

    Publication Year: 1989, Page(s):1345 - 1351
    Cited by:  Papers (175)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    An interconnection network is presented for a massively parallel fine-grained single-instruction, multiple-data (SIMD) system, called the polymorphic-torus, whose design goal is to provide high communication bandwidth under a packaging constraint. This goal is achieved by the polymorphic principle, which injects switches with circuit-switching capability into every node of a base network (e.g. a t... View full abstract»

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  • Token relabeling in a tagged token data-flow architecture

    Publication Year: 1989, Page(s):1225 - 1239
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1172 KB)

    A direct structure access approach called token relabeling scheme is presented in which all array operations can be performed without the use of any intermediary structure memory. The graph constructs for both approaches are described. Four numerical algorithms including fast Fourier transform, bitonic sort, LU decomposition, and matrix multiplication are implemented in both approaches. T... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org