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Semiconductor Manufacturing, IEEE Transactions on

Issue 2 • Date May 1997

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Guest Editorial ICMTS'96

Reactor design considerations for MOCVD growth of thin films

Hybrid optical-electrical overlay test structure

Semi-empirical neural network modeling of metal-organic chemical vapor deposition

Benchmarking semiconductor manufacturing performance using a pairwise-comparison method

Using qualitative observations for process tuning and control [IC manufacture]

Quick address detection of anomalous memory cells in a flash memory test structure

A wafer level monitoring method for plasma-charging damage using antenna PMOSFET test structure

An electrical test structure for the measurement of planarization

Test structures to measure the Seebeck coefficient of CMOS IC polysilicon

Using neural network process models to perform PECVD silicon dioxide recipe synthesis via genetic algorithms

Test structure design for the evaluation of carrier-carrier scattering effect on hole and electron mobilities

Contamination issues in gas delivery for semiconductor processing

Influence of die attachment on MOS transistor matching

Use of test structures for characterization and modeling of inter and intra-layer capacitances in a CMOS process

ICMTS'96

Requirements for contamination control in the gigabit era

Simulation of yield/cost learning curves with Y4

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