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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 1997

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Displaying Results 1 - 18 of 18
  • The Beginnings Of The Symposium On VLSI Circuits

    Publication Year: 1997 , Page(s): 621 - 623
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    Freely Available from IEEE
  • A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

    Publication Year: 1997 , Page(s): 736 - 744
    Cited by:  Papers (228)  |  Patents (62)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    A completely integrated 1.8-GHz low-phase-noise voltage-controlled oscillator (VCO) has been realized in a standard silicon digital CMOS process. The design relies heavily on the integrated spiral inductors which have been realized with only two metal layers and without etching. The effects of high-frequency magnetic fields and losses in the heavily doped substrate have been simulated and modeled with finite-element analysis. The achieved phase noise is as low as -116 dBc/Hz at an offset frequency of 600 kHz, at a power consumption of only 6 mW. The VCO is tuned with standard available junction capacitances, resulting in a 250-MHz tuning range View full abstract»

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  • A 1.5-V, 1.5-GHz CMOS low noise amplifier

    Publication Year: 1997 , Page(s): 745 - 759
    Cited by:  Papers (651)  |  Patents (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-μm CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices View full abstract»

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  • The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory

    Publication Year: 1997 , Page(s): 655 - 661
    Cited by:  Papers (1)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    A charge-share modified (CSM) precharge-level architecture for selective subdataline activation designed to simultaneously achieve high-speed and low-power ferroelectric nonvolatile memories is described. In this architecture, to read the data of only one memory cell destructively, the precharge level of the selected subdataline is modified by charge-sharing between the subdataline and main dataline. This architecture enables high-speed read operations, because the operations of modifying the precharge level and reading the data of memory cells are achieved simultaneously. Three circuit technologies are used in the CSM architecture to increase the operating margin: self-timing precharge circuits which solve the polarization disturbance problem without adding extra signal lines or timing margins, a boosted precharge level technique which increases the signal voltage of the nonvolatile data, and shared dummy cell circuits which improve the precision of the reference voltage over that of a conventional voltage generator. These techniques and circuits are evaluated for a simulated 16-Mb ferroelectric memory. They reduce the access time by 20 ns to 51 ns compared with the conventional architecture, while reducing the memory array current to less than 1% that of the all-subdataline activation technology View full abstract»

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  • A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application

    Publication Year: 1997 , Page(s): 760 - 765
    Cited by:  Papers (12)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-μm CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of ±25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm2, the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter View full abstract»

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  • A compact on-chip ECC for low cost flash memories

    Publication Year: 1997 , Page(s): 662 - 669
    Cited by:  Papers (15)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10-4 to 10-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA View full abstract»

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  • A 700-Mb/s/pin CMOS signaling interface using current integrating receivers

    Publication Year: 1997 , Page(s): 681 - 690
    Cited by:  Papers (38)  |  Patents (101)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    A high speed CMOS signaling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes I-V push-pull drivers, a delay line phase-locked loop (PLL), and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception, a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8 μm CMOS technology achieve transfer rates of 740 Mb/s/pin operating from a 3.3 V supply with a bit error rate of less than 10-14 View full abstract»

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  • Low-voltage, high-speed circuit designs for gigabit DRAMs

    Publication Year: 1997 , Page(s): 642 - 648
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    This paper describes several new circuit design techniques for low VCC regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (ΔVBL ) as well as the VGS margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-μm twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (tRAC) of 28 ns at Vcc=1.5 V and T=25°C has been obtained View full abstract»

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  • A direct digital synthesizer with interpolation circuits

    Publication Year: 1997 , Page(s): 766 - 770
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    This paper presents a direct digital synthesizer (DDS) with no ROM that still produces square waves with low spurious signals. The main features are the interpolation of the analog-converted accumulator contents and the extraction of timing at the points where the interpolated signal is identical to a continuous sawtooth waveform. Experimental results confirm successful frequency synthesizer operation. The output frequency is determined by the frequency control word, and spurious signals present in the accumulator contents are greatly reduced View full abstract»

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  • A 2-GHz 1.6-mW phase-locked loop

    Publication Year: 1997 , Page(s): 730 - 735
    Cited by:  Papers (25)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    This paper describes the design of a 2 GHz 1.6 mW phase-locked loop (PLL) fabricated in an 18 GHz 0.6 μm BiCMOS technology. Employing cross-coupled delay elements and inductive peaking, the circuit merges the oscillator and the mixer into one stage to lower the power dissipation. An experimental prototype exhibits an r.m.s. jitter of 2.8 ps, a tracking range of 100 MHz, and a capture range of 70 MHz while operating from a 3 V supply. The phase noise in the locked condition is -115 dBc/Hz at 400 kHz offset View full abstract»

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  • A high bandwidth constant gm and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems

    Publication Year: 1997 , Page(s): 701 - 712
    Cited by:  Papers (47)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    A new rail-to-rail CMOS input architecture is presented that delivers behavior nearly independent of the common-mode level in terms of both transconductance and slewing characteristics. Feedforward is used to achieve high common-mode bandwidth, and operation does not rely on analytic square law characteristics, making the technique applicable to deep submicron technologies. From the basis of a transconductor design, an asynchronous comparator and a video bandwidth op amp are also developed, providing a family of general purpose analog circuit functions which may be used in high (and low) bandwidth mixed-signal systems. Benefits for the system designer are that the need for rigorous control of common-mode levels is avoided and input signal swings right across the power supply range can be easily handled. A further benefit is that having very consistent performance, the circuits can be easily described in VHDL (or other behavioral language) to allow simulation of large mixed-signal systems. The circuits presented may be easily adapted for a range of requirements. Results are presented for representative transconductor, op amp, and comparator designs fabricated in a 0.5 μm 3.3 V digital CMOS process View full abstract»

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  • A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

    Publication Year: 1997 , Page(s): 691 - 700
    Cited by:  Papers (66)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and r.m.s. jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6 μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin View full abstract»

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  • A CMOS channel-select filter for a direct-conversion wireless receiver

    Publication Year: 1997 , Page(s): 722 - 729
    Cited by:  Papers (33)  |  Patents (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    A highly selective and linear switched-capacitor channel-select filter is fabricated in 1-μm CMOS for a direct-conversion wireless receiver operating in the 902-928 MHz ISM band. The filter selects a 230-kHz wide channel and attenuates by at least 50 dB from 320 kHz to 57 MHz. The input IP3 is +30 dBm, the input-referred noise in the passband is 70 nV/√Hz, and the circuit takes 4.6 mA from a 3.3 V supply. Direct subsampling of the 915 MHz RF input signal by the filter front-end is also demonstrated with only a small degradation in linearity. The input noise voltage is halved in a redesign while keeping the current drain unchanged View full abstract»

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  • A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed

    Publication Year: 1997 , Page(s): 670 - 680
    Cited by:  Papers (9)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm2 and an effective cell size of 1.1 μm2 View full abstract»

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  • A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip

    Publication Year: 1997 , Page(s): 635 - 641
    Cited by:  Papers (7)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    A modular architecture for a DRAM-integrated, multimedia chip with a data transfer rate of 6 to 12 Gbyte/s is proposed. The architecture offers the design flexibility in terms of both DRAM capacity and the logic-memory interface for use in a wide variety of applications. A DRAM macro built from cascadable DRAM bank modules having a 256-kb memory capacity and 128-b I/Os provides flexibility and reconfigurability of DRAM capacity and a high data transfer rate with an area of 6.4 mm2 /Mb. A data transfer circuit (called the “reconfigurable data I/O attachment”), which is attached to the I/O lines of the DRAM macro, provides a flexible logic-memory interface by changing the data-transfer routes between the DRAM macro and logic circuits in real time. A 6.4-Gbyte/s test chip (called the “media chip”) for three-dimensional computer graphics was fabricated to test the proposed design methodology. It integrates an 8-Mb DRAM and four pixel processors on an 8.35×14.6-mm chip by using a 0.4-μm CMOS design rule View full abstract»

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  • 2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell

    Publication Year: 1997 , Page(s): 649 - 654
    Cited by:  Papers (5)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    Nonvolatile memory embedded in microcontrollers has required a 100 ns access time at 2.0 V for mobile information terminals operating with a rechargeable battery. To achieve this, this paper proposes a new ferroelectric nonvolatile memory (FeRAM) architecture that utilizes a bitline-driven read scheme and a nonrelaxation reference cell for high-speed and low-voltage operations, respectively. Using this architecture, FeRAM with a one transistor and one capacitor per bit (1T/1C) cell can achieve 100 ns access time at 2.0 V View full abstract»

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  • Limitations and challenges of multigigabit DRAM chip design

    Publication Year: 1997 , Page(s): 624 - 634
    Cited by:  Papers (33)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (VT) variation and offset voltage of sense amplifiers, reduction in ion-implantation energy and process temperature is essential. Also, the keys in terms of area, speed, stable cell operation, and ease of fabrication are use of low-resistivity multilevel metal wiring and high permittivity materials and three-dimensional memory cells to reduce a difference in height between the memory cell array and the surrounding peripheral circuits. 2) For creation of a high speed, the keys are memory-subsystem technology such as pipeline operation, wide-bit I/O, low-voltage interfaces, and high-density packaging. Embedded DRAM further enhances the speed and throughput by using massively parallel processing of signals on a large number of data-lines and reducing internal bus capacitances. 3) For power reduction, the key continues to be reduction of the data-line dissipating charge through both partial activation of multidivided data-lines and lowering of the data-line voltage. Ultralow-voltage operation, essential to drastic power reduction, can be achieved by subthreshold-current reduction circuits such as source-gate backbiasing, multi-VT, dynamic VT, and node-boosting schemes View full abstract»

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  • A mixed-signal RAM decision-feedback equalizer for disk drives

    Publication Year: 1997 , Page(s): 713 - 721
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    A mixed-signal RAM decision-feedback equalizer (DFE) that operates at 90 Mb/s is described. In the analog domain, the DFE subtracts intersymbol interference caused by the past four outputs. The equalized signal is fed into a nonuniform flash analog-to-digital converter (ADC) to produce the decision output and error signal used to adapt the RAM contents in the digital domain. With a 5 V supply voltage, the power dissipation is 260 mW during steady-state operation. The active area is 4.5 mm2 in a 1 μm CMOS process View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan