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Electron Devices, IEEE Transactions on

Issue 5 • Date May 1997

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Displaying Results 1 - 25 of 37
  • In Memory Of Walter F. Kosonocky

    Publication Year: 1997 , Page(s): 685
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    Freely Available from IEEE
  • Comments on "On the base profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. II. Circuit performance issues"

    Publication Year: 1997 , Page(s): 915 - 917
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (119 KB)  

    For the original paper see ibid., vol. 40, p. 542-555 (1993). The base transit time of the trapezoidal Ge base profile for the SiGe bipolar transistor has been evaluated. The analytical equations derived in the aforementioned paper result in significant error as the trapezoid profile is close to uniform Ge profile. In this work accurate analytical equations are derived. Comparisons between the present analytical predictions and previous published results are given. View full abstract»

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  • Modification of the Einstein equations of majority- and minority-carriers with band gap narrowing effect in n-type degenerate silicon with degenerate approximation and with non-parabolic energy bands

    Publication Year: 1997 , Page(s): 913 - 914
    Cited by:  Papers (1)
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    A new idea is presented for a modification of Einstein equations of the majority- and minority-carriers with the band gap narrowing effect in an n-type degenerate and uniformly-doped silicon with degenerate approximation and with nonparabolic energy bands. It may imply that the Einstein equation may be one factor for the increase of the minority-carrier diffusion coefficient at high doping levels View full abstract»

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  • On the punchthrough phenomenon in submicron MOS transistors

    Publication Year: 1997 , Page(s): 847 - 855
    Cited by:  Papers (4)
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    As the channel length of MOS transistors reduces to the submicron dimension, the punchthrough becomes more of a surface-initiated and gate-controlled phenomenon. A surface diffusion current (Isdif) originates from the injection of minority carriers from the source junction due to the combined effect of drain-induced-barrier-lowering (DIBL) and surface-band-bending (Δφso). The DIBL effect increases rapidly with decreasing channel length. In addition, the extracted Δφso from the punchthrough current indicates that surface space charges at the source edge shift from the accumulation/depletion mode for long submicron devices (≈0.62 μm) to the strong-inversion mode for deep submicron devices (≈0.12 μm). In general, Isdif dominates over the low drain bias range and eventually converts to the bulk space-charge-limited current (Iscl) as the drain bias increases and the source/drain depletion regions connect. The drain bias for this conversion to occur strongly depends on the channel dimension. Only intermediate submicron devices (≈0.37 μm) in this study clearly show both the surface and bulk (space-charge-limited) punchthrough components. For long submicron devices, Isdif essentially dominates, while for deep submicron devices, it converts rapidly to Iscl over the drain bias range investigated. A semi-empirical closed form equation is proposed to describe both Isdif and Iscl and their merging over the entire range of drain bias View full abstract»

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  • Planar 6H-SiC MESFETs with vanadium implanted channel termination

    Publication Year: 1997 , Page(s): 907 - 910
    Cited by:  Papers (2)
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    We use vanadium ion implantation to form a highly resistive surface layer in the wide bandgap semiconductor silicon carbide (SiC). MESFETs are successfully fabricated using this highly resistive layer to isolate gate metal extensions along the channel width from the p-type epilayer. Fabrication and characterization of these devices are described in this paper View full abstract»

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  • Separating the influences of neutral base recombination and avalanche breakdown on base current reduction in SiGe HBT's

    Publication Year: 1997 , Page(s): 901 - 903
    Cited by:  Papers (5)
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    A simple experimental procedure is proposed to determine the separate ranges of reverse collector-base bias where neutral base recombination and avalanche breakdown, respectively, dominate base current reduction in silicon germanium heterojunction bipolar transistors (SiGe HBTs) which exhibit significant neutral base recombination View full abstract»

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  • Simple modeling of coplanar waveguide on thick dielectric over lossy substrate

    Publication Year: 1997 , Page(s): 856 - 861
    Cited by:  Papers (17)
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    We present a simple semi-empirical high-frequency equivalent circuit model to characterize the coplanar waveguide structure, which consists of a relatively thick metal line on very thick polyimide over a lossy substrate such as a Si BiCMOS wafer. Considering the geometric dependence of the conductive loss and the skin effect of the substrate loss, we derive modified models for the equivalent circuit elements. We verify the validity of our model by comparing it with experimental measurements. Our model is simple enough not only to be suitable for efficient circuit simulation but also to be useful for process characterization and design View full abstract»

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  • A novel charge-pumping method for extracting the lateral distributions of interface-trap and effective oxide-trapped charge densities in MOSFET devices

    Publication Year: 1997 , Page(s): 782 - 791
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    A novel charge-pumping method using dc source/drain biases and specified gate waveforms is proposed to extract the lateral distributions of interface-trap and effective oxide-trapped charge densities. The surface potential redistribution due to the oxide-trapped charges is treated by an iteration process in order to accurately determine their lateral distributions. The proposed novel method is feasible for accurately extracting the distributions of interface-trap and effective oxide-trapped charge densities generated by the hot-carrier stress and can be further used to predict the device lifetime View full abstract»

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  • The relevance of fT and fmax for the speed of a bipolar CE amplifier stage

    Publication Year: 1997 , Page(s): 775 - 781
    Cited by:  Papers (5)
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    Expressions relating the bandwidth of a common-emitter (CE) amplifier stage and the small-signal CML gate delay time to directly measurable transistor parameters, such as fT, fmax, and input bandwidth fυ, are presented. They are valid for an arbitrary division of the base resistance and base-collector depletion capacitance into internal and external components. No resistance measurements are needed. It is shown that the transistor input bandwidth fυ is an important figure of merit for the speed of a CE stage. Under a given bias condition, fυ is determined by the base resistance and the cut-off frequency. In most cases the value of the maximum oscillation frequency fmax is only of minor importance. It would therefore be more meaningful to present besides fT also fυ instead of fmax as a figure of merit for transistors for high-speed, low-power analog and digital circuits View full abstract»

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  • Base current relaxation transient in reverse emitter-base bias stressed silicon bipolar junction transistors

    Publication Year: 1997 , Page(s): 792 - 800
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    The base current relaxation transient following reverse emitter-base (EB) bias stress and its effect on time-to-failure (TTF) determination are examined in self-aligned and nonself-aligned silicon bipolar junction transistors (BJTs) with thermal and deposited base oxide. A quantitative model indicates that the transient is due to a reduction of the stress-generated positive charge trapped in the oxide layer near the emitter-base junction due to holes tunneling from oxide hole traps to silicon band states or SiO2/Si interface traps. The neutral oxide hole traps may be quickly recharged through hole tunneling or hole injection into the oxide during further reverse-bias stress. A delay time of ~10-3 s was observed after the termination of stress before base current relaxation begins, which affects the extraction of the ac operation TTF from dc stress measurements View full abstract»

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  • Simulation of submicron double-heterojunction high electron mobility transistors with MINIMOS-NT

    Publication Year: 1997 , Page(s): 700 - 707
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    Simulations and measurements of submicron pseudomorphic high electron mobility transistors (HEMTs) are presented. For the simulations the generic device simulator MINIMOS-NT is used which is capable of dealing with complex device geometries as well as with several physical models represented by certain sets of partial differential equations. A description of the structure of the simulator is given, which shows the basic idea of splitting the device geometry into distinct regions. Within these “segments”, arbitrary material properties and physical models, i.e., partial differential equations, can be defined independently. The segments are linked together by interface models which account for the interface conditions. The simulated characteristics of a HEMT with a gate length of 240 nm are compared with the measured data. Essential physical effects which determine the behavior of the device can be identified in the output and transfer characteristics View full abstract»

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  • Optimum collector width of VLSI bipolar transistors for maximum f max at high current densities

    Publication Year: 1997 , Page(s): 903 - 905
    Cited by:  Papers (1)
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    A simple analytical model for optimum collector epi-layer thickness Wepi to maximize fmax of VLSI bipolar transistors having reach-through collector is reported. Numerical and analytical results for Wepi are compared to verify the validity of our model for the optimum collector epi-layer thickness at high current densities View full abstract»

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  • Modeling effects of electron-velocity overshoot in a MOSFET

    Publication Year: 1997 , Page(s): 841 - 846
    Cited by:  Papers (14)
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    A simple analytical expression to account for electron-velocity overshoot effects on the performance of very short-channel MOSFETs has been obtained. This new model can be easily included in circuit simulators of systems with a huge number of components. The influence of temperature and low-field mobility on the increase of MOSFET transconductance produced by electron-velocity overshoot as channel lengths are reduced can be easily taken into account in our model. The accuracy of this model has been verified by reproducing experimental and simulated data reported by other authors View full abstract»

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  • A temperature all-silicon micro-sensor based on the thermo-optic effect

    Publication Year: 1997 , Page(s): 766 - 774
    Cited by:  Papers (19)
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    A new class of temperature silicon micro-sensors, based on an interferometric optical technique, is presented. The sensing element consists of a planar Fabry-Perot cavity defined on a silicon wafer by highly anisotropic reactive ion etching, and is therefore suitable for full integration with other standard opto- and micro-electronic devices. Preliminary temperature measurements have been performed with the temperature resolutions predicted by the theory. The limit performances, in terms of resolution, speed of operation and energy dissipation of this class of sensors are discussed in detail. In particular, a final temperature resolution of 0.064°C is expected for a low loss interferometric cavity, with a settling time of 150 ns and a 0.2% readout error. An energy resolution as low as 30 nJ is also estimated View full abstract»

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  • Back-gated CMOS on SOIAS for dynamic threshold voltage control

    Publication Year: 1997 , Page(s): 822 - 831
    Cited by:  Papers (36)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipation becomes a significant portion of the total power consumption. This is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods, a dynamic threshold voltage control scheme is proposed. A novel Silicon-On-Insulator (SOI)-based technology called Silicon-On-Insulator-with-Active-Substrate (SOIAS) was developed whereby a back-gate is used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage, a reduction of 3-4 decades in subthreshold leakage current was measured View full abstract»

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  • Effects of silicon layer properties on device reliability for 0.1-μm SOI n-MOSFET design strategies

    Publication Year: 1997 , Page(s): 815 - 821
    Cited by:  Papers (1)
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    We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (1016 cm-3) channel and 2) a heavily-doped (1018 cm-3) channel. For each design, the silicon layer thicknesses (TSi) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO2 barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in TSi results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead View full abstract»

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  • Optimization of the anti-parallel diode in an IGBT module for hard-switching applications

    Publication Year: 1997 , Page(s): 879 - 886
    Cited by:  Papers (8)
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    This paper presents a novel P-i-N diode which is suitable to be used as an anti-parallel diode in an IGBT module. It is shown that the switching performance of the module is significantly improved with the new diode structure, under hard-switching conditions. Diode performance in commercially available IGBT modules is studied under hard-switching conditions, both experimentally and using a finite element based device simulator. The device simulator is then used to study and compare the performance of the new diode structure with commercially available devices. It is shown that the new structure gives superior switching performance at the cost of a small increase in its on-state voltage drop. It is also shown that the switching characteristics of the new diode show a dramatic improvement over the conventional P-i-N diode at high temperatures View full abstract»

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  • Characteristics of a In0.52(AlxGa1-x )0.48As/In0.53Ga0.47 As(0⩽x⩽1) heterojunction and its application on HEMT's

    Publication Year: 1997 , Page(s): 708 - 714
    Cited by:  Papers (4)
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    The quaternary In0.52(AlxGa1-x) 0.48As compound on InP substrates is an important material for use in optoelectronic and microwave devices. We systematically investigated the electrical properties of quaternary In0.52(AlxGa1-x)0.48As layers, and found a 10% addition of Ga atoms into the InAlAs layer improves the Schottky diode performance. The energy bandgap (Eg ) for the In0.52(AlxGa1-x)0.48As layer was (0.806+0.711x) eV, and the associated conduction-band discontinuity (ΔEc), in the InAlGaAs/In0.53Ga0.47 As heterojunction, was around (0.68±0.01)ΔEg . Using this high quality In0.52(Al0.9Ga0.1)0.48As layer in the Schottky and buffer layers, we obtained quaternary In0.52(Al0.9Ga0.1)0.48As/In 0.53Ga0.47As HEMTs. This quaternary HEMT revealed excellent dc and microwave characteristics. In comparison with the conventional InAlAs/InGaAs HEMT's, quaternary HEMT's demonstrated improved sidegating and device reliability View full abstract»

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  • Small-signal distributed model for GaAs HBT's and S-parameter prediction at millimeter-wave frequencies

    Publication Year: 1997 , Page(s): 723 - 732
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    The development of a new Heterojunction Bipolar Transistor (HBT) distributed electrical model suitable for millimeter-wave applications is reported. Each section of the distributed model is composed of an active slice, modeled as an intrinsic HBT, and connected to other slices through a passive connecting network. It is shown that, for large size and high power HBT's, a distributed model is more accurate than a lumped-element one. This is confirmed by comparing the S-parameters calculated using both models to the measured data over a wide frequency band. It is also shown that the distributed model allows accurate prediction of S-parameter behavior at higher frequencies where the lumped model may not have accurate prediction View full abstract»

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  • Electrothermal effects during unclamped inductive switching (UIS) of power MOSFET's

    Publication Year: 1997 , Page(s): 874 - 878
    Cited by:  Papers (13)
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    The ruggedness of scaled power DMOSFET's under unclamped inductive switching (UIS) conditions is studied using an advanced two-dimensional (2-D) device simulator. It is shown that at the onset of device turnoff, significant self-heating occurs within the intrinsic device which leads to an increase in the avalanche breakdown voltage of the device. The self-heating mechanism is incorporated by self-consistently solving heat generation and diffusion equations with semiconductor charge balance and transport equations. The power module is modeled by accounting for various thermal resistances including those contributed by the package, contact metallization and intrinsic device material. The simulation results are compared with extensive UIS measurements and it is shown that the simulations can be used to identify local “hot spots” and the design and process parameters that lead to thermal runaway View full abstract»

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  • A 3-terminal model for diffused and ion-implanted resistors

    Publication Year: 1997 , Page(s): 809 - 814
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    In this paper, we present a new, physically based 3-terminal model for diffused and ion-implanted resistors. The model accounts for the effects of geometry, temperature, and bias, and includes parasitic p-n junction diodes. The junction depletion capacitances are distributed to model high-frequency behavior accurately View full abstract»

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  • CMOS-circuit degradation analysis using optical measurement of the substrate current

    Publication Year: 1997 , Page(s): 910 - 912
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (80 KB)  

    This paper analyzes the photon emission under AC operation caused by hot carriers in MOSFET's, and determines the lifetime of CMOS circuits by means of a direct photon count measurement that replaces the traditional electrical measurement of the substrate current. This is made possible by the linear relation between the substrate current and the photon count at about 830 nm for all operating values of gate voltage. The paper presents an application of this method to monitor the long term degradation of the delay time of CMOS inverters and highlights the advantages of this noninvasive technique which can therefore be used to predict the lifetime also of devices in which the substrate current cannot be measured directly, as in SOI devices View full abstract»

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  • Modeling of output resistance in SiGe heterojunction bipolar transistors with significant neutral base recombination

    Publication Year: 1997 , Page(s): 693 - 699
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    A simple compact model, suitable for circuit simulations, is derived which enables quantitative determination of the impact of neutral base recombination on the small signal ac output resistance of SiGe HBT's for arbitrary base ac drive conditions. The model uses existing SPICE parameters which are routinely extracted from bipolar transistors plus an additional model parameter which can be extracted from a proposed experimental technique involving output resistance measurements under base ac voltage and current drive conditions. The modeling approach also enables the forward and reverse base transit times to be related to transistor small signal ac output resistance by a simple analytic expression. The currently accepted expression for the r μ parameter, which is used to model neutral base recombination in the ac hybrid-π equivalent circuit, is shown to be incorrect and is replaced by a new correct expression. Numerical simulations of a SiGe HBT structure which exhibits neutral base recombination are used to verify the validity of the model View full abstract»

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  • A new equivalent MOSFET representation of a HEMT to analytically model nonlinear charge control for simulation of HEMT devices and circuits

    Publication Year: 1997 , Page(s): 862 - 868
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    It is shown that, from the point of view of the behavior of the charge and position of the Two-Dimensional Electron Gas (2-DEG) as a function of gate-source and drain-source voltages, the complex High Electron Mobility Transistor (HEMT) can be regarded as a simple Buried-Channel (BC) MOSFET. Thus, the characteristics of a HEMT, namely channel charge and capacitance/transconductance as a function of gate voltage below and above threshold are akin those of a BC MOSFET. Hence, there are discrepancies in the conventional Surface Channel MOSFET-like approach to HEMT modeling. Existing simple BC MOSFET dc and ac models can be used for on-paper analysis and computer aided simulation of HEMT devices and circuits, if the HEMT is represented by an equivalent BC MOSFET as derived in this paper. The new representation can be useful for modeling of short-channel HEMT phenomena View full abstract»

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  • Determination of bandgap narrowing and parasitic energy barriers in SiGe HBT's integrated in a bipolar technology

    Publication Year: 1997 , Page(s): 715 - 722
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    This paper describes a method for characterizing the bandgap narrowing and parasitic energy barrier in SiGe heterojunction bipolar transistors (HBTs), fabricated using a single-polysilicon self-aligned bipolar process. From a comprehensive study of the temperature dependence of the collector current, the bandgap narrowing in the base due to germanium has been dissociated from that due to the heavy dopant concentration. The same approach has been used to characterize the height and width of parasitic energy barriers which appear when boron out-diffusion from the SiGe base is present. The method has been applied to SiGe heterojunction bipolar transistors fabricated using a single polysilicon, self-aligned, bipolar process, as well as mesa transistors. The experimental results show that small geometry transistors have degraded collector currents due to boron out-diffusion around the perimeter of the emitter. This behavior has been explained by accelerated boron diffusion due to point defects generated during the extrinsic base implant. The values of undoped SiGe spacer thickness needed to suppress the parasitic energy barrier are described. Finally, high-frequency results are reported, which correlate the frequency transition to these parasitic energy barriers View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego