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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Apr 1997

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Displaying Results 1 - 17 of 17
  • A low-voltage ultra-low-power translinear integrator for audio filter applications

    Publication Year: 1997 , Page(s): 577 - 581
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB)  

    In this paper, the design and measurement of a l-V translinear integrator and its application in a controllable second-order lowpass filter for hearing instruments is presented. A semicustom version of the filter has been integrated in a standard 2-μm, 7-GHz, bipolar IC process and operates at voltages down to 1 V, consumes only 6 μA, and has a dynamic range of 57 dB for a total harmonic distortion below 2%. Its cutoff frequency is linearly adjustable in octaves from 1.6 to 8 kHz View full abstract»

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  • A high-performance, low-power complementary coupled BiCMOS circuit

    Publication Year: 1997 , Page(s): 610 - 612
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    Reported is a new complementary technique of full-swing BiCMOS circuit design which, though employs a p-n-p, allows the use of n-p-n-only drivers. The simulated results of this new circuit compare favorably among several representative BiCMOS circuits View full abstract»

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  • NRZ timing recovery technique for band-limited channels

    Publication Year: 1997 , Page(s): 514 - 520
    Cited by:  Papers (20)  |  Patents (36)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    Nonreturn-to-zero (NRZ) data, when transmitted over band-limited channels, suffer from the lack of zero crossings because the elongated tail of each pulse interferes with subsequent ones, causing intersymbol interference (ISI). An NRZ timing recovery technique working with a decision-feedback equalizer (DFE) recovers the clock from the equalized waveform and enables data transmission at a rate ten times higher than the channel bandwidth. The proposed timing recovery technique uses a data-triggered low-jitter phase detector to sustain phase locking even with 600 missing transitions, A data rate of 30 Mb/s in 3-MHz bandwidth is demonstrated with a peak-peak clock jitter of 2 ns using 2-μm CMOS View full abstract»

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  • A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation

    Publication Year: 1997 , Page(s): 582 - 586
    Cited by:  Papers (24)  |  Patents (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (108 KB)  

    This paper describes a phase-locked loop (PLL) based frequency synthesizer. The voltage-controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and operation over a wide range of power supply voltage. A programmable charge pump circuit automatically configures the loop gain and optimizes it over the whole frequency range. The measured PLL frequency ranges are 0.3-165 MHz and 0.3-100 MHz at 5 V and 3 V supplies, respectively (the VCO frequency is twice PLL output). The peak-to-peak jitter is 81 ps (13 ps rms) at 100 MHz. The chip is fabricated with a standard 0.8-μm n-well CMOS process View full abstract»

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  • Substrate coupling evaluation in BiCMOS technology

    Publication Year: 1997 , Page(s): 598 - 603
    Cited by:  Papers (15)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    The magnitude of switching noise coupled through common substrate in BiCMOS technology is analyzed. Noise dependence on collector resistance and buried layer doping of the noisy bipolar junction transistor (BJT) is obtained by means of simulation. It is observed that trends are different depending on bipolar transistor biasing: in common-collector, a low collector resistance is desired, while in common-emitter biasing, large values of Rc make the transistor less noisy. A test chip is fabricated in 3-μm BiCMOS technology to measure the substrate coupling produced by different BICMOS inverter gates. These experimental measurements show that noise increases with transistor size and collector resistance. Dependence on distance and speed of signal are also obtained, together with the effect of a guard ring View full abstract»

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  • A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wireless communications networks

    Publication Year: 1997 , Page(s): 521 - 525
    Cited by:  Papers (11)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    This paper concerns the design consideration, fabrication process, and performance results for an ultra-broadband, low-voltage, low-power, BiCMOS-based transceiver chip for cellular-satellite-LAN wireless communication networks. The transceiver chip incorporates an RF amplifier, a Gilbert down-mixer, and an IF amplifier in the receive path, and an IF amplifier, a Gilbert up-mixer, and an RF amplifier in the transmit path. For an RF frequency in the 1-10 GHz band and an IF frequency in the 100-1000 MHz band, the developed transceiver chip consumes less than 60 mW at 2 V, to yield a downconversion gain of 40 dB at 1 GHz and 10 dB at 10 GHz and an upconversion gain of 42 dB at 1 GHz and 11 dB at 10 GHz. To avoid possible start-up problems caused during “stand-by” to “enable” mode transition, a simple switching technique is employed for enabling either the receive or the transmit path, by changing the value of a reference voltage applied to both the down- and the up-mixers. While the developed transceiver chip exhibits the best performance for a dc supply voltage of 2 V, it shows a graceful degradation for a ±0.15 V voltage deviation. The transceiver's chip size is 1.04 mm×1.04 mm View full abstract»

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  • The design of rotation-invariant pattern recognition using the silicon retina

    Publication Year: 1997 , Page(s): 526 - 534
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    A new rotation-invariant pattern recognition system is proposed and analyzed. In this system, silicon retina cells capable of image sensing and edge extraction are used so that the system can directly process images from the real world without an extra edge detector. The rotation-invariant discrete correlation function is modified and implemented in the silicon retina structure by using the current summation. Simulation results have verified the correct function of the proposed system. Moreover, an experimental chip to implement the proposed system with a 32×32 cell array has been designed and fabricated in 0.8-μm n-well CMOS process. Experimental results have successfully shown that the system works well for the arbitrary orientation pattern recognition View full abstract»

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  • A low-power, low-cost bipolar GPS receiver chip

    Publication Year: 1997 , Page(s): 587 - 591
    Cited by:  Papers (10)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    A low-power, low-cost, integrated global positioning by satellite (GPS) receiver is described. It operates from a single 2.7-5.5 V supply with a nominal current consumption of only 27 mA. Furthermore, there is no need for expensive external surface acoustic wave (SAW) filters or a radio frequency voltage-controlled oscillator (VCO) module; only a low frequency reference clock (temperature compensated crystal oscillator (TCXO) or crystal), varactor diodes and standard passive elements are necessary for full operation. The chip is compatible with baseband chips requiring 1 fo (1.023 MHz) and 4 fo signal frequencies. The device has been integrated using a 15-GHz silicon bipolar technology View full abstract»

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  • Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance

    Publication Year: 1997 , Page(s): 574 - 576
    Cited by:  Papers (24)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (64 KB)  

    Adding on-chip decoupling capacitance has become a popular method to reduce dI/dt noise in integrated circuits. The most area-efficient realization of on-chip capacitance in a standard CMOS process is to use the gate capacitance of MOS transistors. In this paper, the inevitable parasitic resistance of an MOS transistor is estimated, which is important for two reasons. The resistive noise caused by this parasitic must be kept low, and, if properly sized, this resistance can be used to dampen potential resonance oscillations View full abstract»

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  • Phase-correcting feedback system for class E power amplifier

    Publication Year: 1997 , Page(s): 544 - 549
    Cited by:  Papers (15)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    A phase-correcting feedback system which reduces the AM-to-PM distortion of Class E power amplifiers for wireless communication is presented in this paper. It comprises a novel limiting amplifier, a phase detector, and a phase shifter all operating at 835 MHz. The phase-correcting feedback together with a Class E power amplifier were fabricated in a 0.8-μm GaAs MESFET process. The limiting amplifier has a phase error less than 2.5°. The phase detector and phase shifter have a sensitivity of 10 mV/degree and 80°/V, respectively. The Class E power amplifier delivers 26.5 dBm to the load with a power added efficiency of 67%. The phase correcting feedback system reduces the 30° phase distortion of the Class E amplifier down to 4°, and its total power dissipation is 21.5 mW View full abstract»

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  • Low-power BiCMOS circuits for high-speed interchip communication

    Publication Year: 1997 , Page(s): 604 - 609
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    A universal BiCMOS low-voltage-swing transceiver (driver/receiver) with low on-chip power consumption is reported. Using a 3.3 V supply, the novel transceiver can drive/receive signals from several low-voltage-swing transceivers with termination voltages ranging from 5 V down to 2 V and frequencies well above 1 GHz. Measured results of test circuits fabricated in 0.8-μm BiCMOS technology are also presented View full abstract»

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  • Noise margin enhancement in GaAs ROM's using current mode logic

    Publication Year: 1997 , Page(s): 592 - 597
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    Two different techniques that allow the implementation of embedded ROMs using a conventional GaAs MESFET technology are presented. The first approach is based on a novel circuit structure named low leakage current FET circuit (L2FC), which reduces significantly subthreshold currents. The second approach is based on pseudo current mode logic (PCML) which is by far the best choice in terms of noise margin levels. This characteristic is found to be the key factor when implementing GaAs ROM's because of its degradation as the number of word lines is increased. A 5-Kb ROM and a 2-Kb ROM were designed giving delays in the order of 2 ns and less than 1 ns, respectively. The results demonstrate the effectiveness of these techniques and their significance toward improving the noise margin View full abstract»

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  • Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems

    Publication Year: 1997 , Page(s): 563 - 573
    Cited by:  Papers (47)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type of ratioless circuit, and it also provides superior performance with less power dissipation and better silicon area tradeoff. The basic DCVSPG design technique, the methodology for optimization, and synthesis of the pass-gate logic tree are described. The standard cell library development taking advantage of the dual-rail outputs of DCVSPG gates is also discussed. The performance comparisons with other existing pass-gate circuit techniques [complimentary pass-transistor logic (CPL), double pass-transistor logic (DPL), and swing restored pass-transistor logic (SRPL)] are presented. For more robust design, the DCVSPG with inverter buffers is also the best choice. A Viterbi macro design using the DCVSPG circuit technique is demonstrated. The process that the design is based upon is a 0.5-μm CMOS technology with 0.25-μm effective channel length and five layers of metal. This macro can run up to 500 MHz at the nominal process condition. In comparison with other existing dynamic circuit techniques, the results also clearly show that the dynamic DCVSPG has the superior power-delay performance View full abstract»

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  • An analog VLSI neural network with on-chip perturbation learning

    Publication Year: 1997 , Page(s): 535 - 543
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    An analog very large scale integration (VLSI) neural network intended for cost-sensitive, battery-powered, high-volume applications is described. Weights are stored in the analog domain using a combination of dynamic and nonvolatile memory that allows both fast learning and reliable long-term storage. The synapse occupies 4.9 K μm2 in a 2-μm technology. On-chip controlled perturbation-based gradient descent allows fast learning with very little external support. Other distinguishing features include a reconfigurable topology and a temperature-independent feedforward path. An eight-neuron, 64-synapse proof-of-concept chip reliably solves the exclusive-or problem in ten's of milliseconds and 4-b parity in hundred's of milliseconds View full abstract»

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  • The delay vernier pattern generation technique

    Publication Year: 1997 , Page(s): 551 - 562
    Cited by:  Papers (9)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    The authors describe a new technique for generating an arbitrary digital data stream with very fine timing resolution. Note that this timing resolution specifies the output edge placement precision, not the bit rate. The resolution is determined by the difference between two propagation delays rather than by an absolute delay. Because this difference can be made very small, the circuit, called the delay vernier generator, can achieve unprecedented timing resolution in a particular circuit technology. Also, this very precise timing is obtained without requiring an extremely high speed clock. The generator architecture includes delay-locked loop calibration mechanisms to compensate for process and temperature variations. A prototype chip was fabricated in a 1.2-μm CMOS technology, and measurements confirmed that resolutions as fine as 100 ps can be achieved reliably View full abstract»

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  • A CMOS continuous-time Gm-C filter for PRML read channel applications at 150 Mb/s and beyond

    Publication Year: 1997 , Page(s): 499 - 513
    Cited by:  Papers (46)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    Design techniques for equiripple phase CMOS continuous-time filters are presented, and their integration within a partial-response maximum likelihood (PRML) disk drive read channel is discussed. A programmable seven-pole two asymmetric zero filter implementation is described based on a new transconductance (Gm) cell. The impact of integrator finite output impedance, excess phase, and other implementation related nonidealities is discussed. A filter tuning circuit that requires an accurate time base but no external components is presented. The filter has a cutoff frequency (fc) range of 6-43 MHz, where fc is the -3 dB point of the magnitude transfer function with the two zeros set to infinity. Also, with finite zeros it is able to provide up to 12 dB of boost which is defined as the maximum value of the magnitude transfer function referred to dc. The group delay ripple stays within ±2% for frequencies below 1.75 f c. The cutoff frequency exhibits a 650 ppm/°C temperature dependency and a variation of ±1%/V with the power supply. Total harmonic distortion (THD) values are below -40 dB at twice the nominal operating input voltage (Vnominal=320 mV peak-to-peak differential), and the dynamic range exceeds 60 dB (for a maximum input signal of 640 mV peak-to-peak differential, maximum bandwidth setting, and no boost). Both the filter and a tuning circuit were implemented in a 0.6-μm single-poly triple-metal n-well CMOS process. They consume 90 mW from a single 5 V power supply and occupy an area of 0.8 mm2 View full abstract»

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  • A 1-GHz bipolar class-AB operational amplifier with multipath nested Miller compensation for 76-dB gain

    Publication Year: 1997 , Page(s): 488 - 498
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    A 1-GHz operational amplifier with a gain of 76 dB while driving a 50-Ω load is presented. The equivalent input noise voltage is as low as 1.2 nV/√Hz. This combination of extremely high bandwidth, high gain, and low noise is the result of a three-stage all-n-p-n topology combined with a multipath nested Miller compensation. Using 10-GHz fT n-p-n transistors, the realizable bandwidth could be of the order of 2-3 GHz. However, bond-wire inductances restrict the useful bandwidth to 1 GHz. The amplifier occupies an active area of 0.26 mm2 and has been realized in the bipolar part of a 1-μm BiCMOS process View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan