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Electron Devices, IEEE Transactions on

Issue 4 • Date Apr 1997

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Displaying Results 1 - 25 of 25
  • High-energy and recombination-induced electroluminescence of InAlAs/InGaAs HEMT's lattice-matched to InP substrates

    Publication Year: 1997 , Page(s): 513 - 519
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    We report room-temperature measurements of the high-energy electroluminescence (EL) of InAlAs/InGaAs HEMT's lattice-matched to InP substrates. We found that both the carrier temperature and the intensity obtained from the EL signal for the 1.4-1.7 eV energy range drastically increases with increasing the variation in the potential at the drain edge in the channel. The observed features are consistent with the results of the spatial distribution measurement, which indicates that the EL comes from the drain edge. We further compared the bias-voltage dependence of the high-energy EL and the recombination-induced EL measured for the same device, and discussed the origin and the threshold energy of the respective luminescent processes View full abstract»

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  • Electrical and luminescent characteristics of a-SiC:H p-i-n thin-film LED'S with graded-gap junctions

    Publication Year: 1997 , Page(s): 565 - 571
    Cited by:  Papers (2)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    a-SiC:H p-i-n thin-film LED's (TFLED's) containing a single graded-gap p-i-n junction (SG) or double graded-gap p-i-n and i-n junctions (DG) have been postulated and fabricated successfully on indium-tin-oxide (ITO)-coated glass substrates, with a plasma-enhanced chemical vapor deposition (PECVD) system. Some important characteristics and related physics of these two types of TFLED's are presented and discussed. At an injection current density (J) of 600 mA/cm2, the brightness (B) of the SG and DG TFLED's obtained were 30 and 207 cd/m2, respectively. This significant improvement of brightness, as compared to those of the previously reported TFLED's with a highest brightness of 20 cd/m2, could be ascribed to the reduced interface states with the graded-gap junctions, lower contact resistance between ITO and the p-layer due to plasma treatment of ITO prior to p-layer deposition, post metallization annealing of thermally evaporated Al on n-layer, and higher optical gaps (Eopt's) of the doped layers employed. The slopes of the nearly linear B-J relationships show a diode factor very close to unity for the fabricated SG and DG TFLED's. This implies that the electroluminescence (EL) mechanism of these TFLED's might be a tail-to-tail-state recombination. In addition, the conduction currents of these TFLED's are almost temperature dependent, and that of the DG TFLED might consist of an ohmic current and a space-charge-limited current (SCLC) within the lower and higher applied-bias regions, respectively View full abstract»

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  • An improved NMOS AC hot-carrier lifetime prediction algorithm based on the dominant degradation asymptote

    Publication Year: 1997 , Page(s): 651 - 658
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    This study presents a new algorithm for improved prediction of AC hot-carrier lifetime. It is based on identifying and projecting the dominant degradation asymptote. The algorithm accounts for the stress-bias dependence of the hot-carrier degradation rate and the nonlinearity of the degradation time-dependence. Detailed model parameter extraction and lifetime prediction procedures are explained, and applications of the new algorithm demonstrated. Significant differences in the predicted AC lifetimes are found between the existing and the new algorithms over a wide range of CMOS inverter design parameters, such as the input ramp rate and the load capacitance View full abstract»

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  • A novel InGaP/GaAs S-shaped negative-differential-resistance (NDR) switch for multiple-valued logic applications

    Publication Year: 1997 , Page(s): 520 - 525
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    In this paper, a novel InGaP/GaAs multiple S-shaped negative-differential-resistance (NDR) switch based on a heterostructure-emitter bipolar transistor (HEBT) structure is fabricated and demonstrated. An interesting multiple NDR phenomenon resulting from an avalanche multiplication and successive two-stage barrier lowering process is observed under the inverted operation mode. The three-terminal-controlled and temperature-dependent NDR characteristics are also investigated. In addition, a typical transistor performance is found under the normal operation mode. Consequently, owing to the presented different stable operation points and transistor action, the studied device shows a good potential for multiple-valued logic and analog amplification circuit applications View full abstract»

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  • An optical modulator prepared by silicon micromachining and thermal bonding

    Publication Year: 1997 , Page(s): 572 - 576
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    An optical modulator using silicon micromachining and thermal bonding is reported. It consists of a pn junction with an optical cavity formed by wafer bonding between n-type and p-type silicon. The cavity is prepared by a thin n-type silicon membrane covering a step with well-controlled dimensions in p-type silicon. Light transmitted through or reflected by the device can be modulated by a second light source with shorter wavelength View full abstract»

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  • Fowler-Nordheim stress degradation in gate oxide: results from gate-to-drain capacitance and charge pumping current

    Publication Year: 1997 , Page(s): 681 - 683
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    The buildup of positive oxide charge and interface trap charge, due to Fowler-Nordheim stress, is observed in the gate-drain overlap region of the MOSFET. Results from gate-to-drain capacitance and charge pumping current show a steady increase in positive charge near the anode interface. Interface trap generation becomes significant when injected electron fluence exceeds ~1014 cm-2, and dominates net charge creation at higher fluence View full abstract»

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  • Potential design and transport property of 0.1-μm MOSFET with asymmetric channel profile

    Publication Year: 1997 , Page(s): 595 - 600
    Cited by:  Papers (26)  |  Patents (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    This paper describes potential design and transport property of a 0.1-μm n-MOSFET with asymmetric channel profile, which is formed by the tilt-angle ion-implantation after gate electrode formation. The relation between device performance and transport property of the asymmetric 0.1-μm device is explored by Monte Carlo simulations, and measured electrical characteristics. The self-consistent Monte Carlo device simulation coupled with a process simulator reveals higher electron velocity at the source end of the channel and velocity overshoot at the source side of the channel, and the smaller high-energy tail of the distribution in the drain. This transport property creates high drain current, large transconductance, and low substrate current of the 0.1-μm n-MOSFET with asymmetric channel profile View full abstract»

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  • Electrical characterization of ultra-shallow junctions formed by diffusion from a CoSi2 layer

    Publication Year: 1997 , Page(s): 526 - 534
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    Ultra-shallow p+/n and n+/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi2 was implanted with As or with BF2 and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 -10 A/cm2 for p+/n and 2.7×10-9 A/cm2 for n+/p, respectively. The temperature dependence of the reverse current in the p +/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n+/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p+ /n junctions have an ideal behavior, while the n+/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi2, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n+/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness View full abstract»

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  • Spatial limitations to the application of the lucky-drift theory of impact ionization

    Publication Year: 1997 , Page(s): 659 - 663
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    Multiplication characteristics predicted by the lucky-drift (LD) theory of impact ionization are compared to experimental results on a range of thin GaAs PIN diodes with i-region thicknesses, w, from 1 μm down to 0.025 μm. Whereas lucky-drift and experimental results are in agreement for w⩾0.1 μm, significant differences are observed for thinner structures where nonlocal effects are important. Multiplication characteristics predicted by Monte-Carlo (MC) and lucky-drift simulations which use the same material parameters and produce the same bulk ionization rates are also compared and differences are again found in the multiplication characteristics of thinner structures. These differences are attributed to the lucky-drift description of carrier transport and establish a lower spatial limit to the application of this theory View full abstract»

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  • Effect of doping on the reliability of GaAs multiple quantum well avalanche photodiodes

    Publication Year: 1997 , Page(s): 535 - 544
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    The effect of various doping methods on the reliability of gallium arsenide/aluminum gallium (GaAs/AlGaAs) multiple quantum well (MQW) photodiode (APD) structures fabricated by molecular beam epitaxy is investigated. Reliability is examined by accelerated life tests by monitoring dark current and breakdown voltage. Median device lifetime and the activation energy of the degradation mechanism are computed for undoped, doped-barrier, and doped-well APD structures. Lifetimes for each device structure are examined via a statistically designed experiment. Analysis of variance (ANOVA) shows that dark current is affected primarily by device diameter, temperature and stressing time, and breakdown voltage depends on the diameter, stressing time, and APD type. It is concluded that the undoped APD has the highest reliability, followed by the doped-well and doped-barrier devices, respectively. To determine the source of the degradation mechanism for each device structure, failure analysis using the electron-beam induced current method is performed. This analysis reveals some degree of device degradation caused by ionic impurities in the passivation layer, and energy-dispersive spectrometry subsequently verifies the presence of ionic sodium as the primary contaminant. However since all device structures are similarly passivated, sodium contamination alone does not account for the observed variation between the differently doped APD's. This effect is explained by dopant migration during stressing, which is verified by free carrier concentration measurements using the capacitance-voltage (C-V) technique View full abstract»

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  • Scaled silicon MOSFET's: universal mobility behavior

    Publication Year: 1997 , Page(s): 577 - 583
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    We use a fully quantum-mechanical model to study the inversion layer mobility in a silicon MOS structure. The importance of depletion charge and surface-roughness scattering on the effective electron mobility is examined. The magnitude of the mobility is found to be considerably reduced by both depletion charge and interface-roughness scattering. The appropriate weighting coefficients a and b for the inversion and depletion charge densities in the definition of the effective electric field, which eliminate the doping dependence of the effective electron mobility, are also calculated. These are found to differ from the commonly used values of 0.5 and 1. In addition, the weighting coefficient for the depletion charge density is found to be significantly influenced by the actual shape of the doping profile and can be either >1 or <1 View full abstract»

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  • A selective epitaxial SiGe/Si planar photodetector for Si-based OEIC's

    Publication Year: 1997 , Page(s): 545 - 550
    Cited by:  Papers (15)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A P-i-N SiGe/Si superlattice photodetector with a planar structure has been developed for Si-based opto-electronic integrated circuits. To make the planar structure, a novel SiGe/Si selective epitaxial growth technology which uses cold wall ultrahigh-vacuum/chemical vapor deposition has been newly developed. The P-i-N planar SiGe/Si photodetector has an undoped 30-Å Si0.9Ge0.1/320-Å Si, 30 periods, superlattice absorption layer, a 0.1-μm P-Si buffer layer, and a 0.2-μm P+-Si contact layer on a bonded silicon-on-insulator (ηext). The bonded SOI is used to increase the external quantum efficiency (ηext) of the photodetector. Moreover, a 63-μm deep/128-μm wide trench, to achieve simple and stable coupling of an optical fiber to the photodetector, is formed in the silicon chip. The P-i-N planar photodetector exhibits a high ηext of 25-29% with a low dark current of 0.5 pA/μm2 and a high-frequency photo response of 10.5 GHz at λ=0.98 μm View full abstract»

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  • High-field transport of inversion-layer electrons and holes including velocity overshoot

    Publication Year: 1997 , Page(s): 664 - 671
    Cited by:  Papers (12)  |  Patents (101)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    In this paper, we experimentally address the effect of a wide range of parameters on the high-field transport of inversion-layer electrons and holes. The studied parameters include substrate doping level, surface micro-roughness, vertical field strength, nitridation of the gate oxide, and device channel length. We employ special test structures built on Silicon-On-Insulator (SOI) and bulk wafers to accurately measure the high-field drift velocity of inversion-layer carriers. Our findings point to electron velocity overshoot at room temperature, dependence of electron and hole saturation velocities on nitridation of the gate oxide, dependence of the high-field drift velocity on the effective vertical field, and relative insensitivity of electron and hole mobility and saturation velocity to moderate surface roughness View full abstract»

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  • Impact of Ge implantation on the electrical characteristics of TiSi 2 p+/n shallow junctions with an a-Si (or a poly-Si) buffer layer

    Publication Year: 1997 , Page(s): 601 - 606
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    A new technology for forming a titanium-silicide shallow junction by combining germanium implantation with an amorphous-silicon (or a poly-silicon) buffer layer has been proposed for MOSFETs. The use of a buffer layer between Ti and Si can avoid the consumption of bulk-silicon and the recession of TiSi2 film into the source/drain junctions during the silicidation process. In this study, the important role of germanium-implantation on the formation of TiSi2 contacted p+/n junctions was examined. After subsequent implantation of Ge+ and B+ into the TiSi2 film, samples were annealed at different temperatures to form p +/n junctions and C54-TiSi2. Since the penetration of titanium atoms was suppressed due to the germanium-implantation, the periphery leakage and the generation leakage were improved and TiSi2/Si interfaces were even smooth. Therefore, p+/n junctions with a very low leakage current (0.192 nA/cm 2 at -5 V) and an excellent forward ideality factor (n≈1.002) can be obtained. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth is 400 View full abstract»

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  • Effects of quasi-ballistic base transport on the high-frequency characteristics of bipolar transistors

    Publication Year: 1997 , Page(s): 618 - 626
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    High-frequency transport in bipolar transistors with quasi-ballistic base widths (on the order of a minority-carrier scattering length) is examined by using the approach of Grinberg and Luryi (1992) to solve the Boltzmann transport equation (BTE). By considering the phase angle of the dynamic distribution function in wave-vector space, it is shown that the ballistic mechanism of decay in the common-base current gain becomes important even for base widths in the quasi-ballistic regime. Simple expressions, which correctly yield both the magnitude and phase of all the forward characteristics, as predicted by the BTE, up to the intrinsic transit frequency, are found by combining the results from a one-flux approach with the well-known expressions of Thomas and Moll (1958). Expressions for the reverse small-signal parameters are also found by applying a “moving boundary condition” to the basic one-flux equations of Shockley (1962) View full abstract»

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  • LOCOS-induced stress effects on thin-film SOI devices

    Publication Year: 1997 , Page(s): 646 - 650
    Cited by:  Papers (21)  |  Patents (44)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    LOCOS-induced stress effects on thin-film SOI devices are investigated. We show that as the field oxide thickness increases, degradation (enhancement) of nMOSFET's (pMOSFET's) I-V characteristics becomes increasingly pronounced. The total degradation or enhancement of I-V characteristics can reach ~40% of drive current for devices under certain processing conditions. Estimated stress results using four-point bending measurement show that the stress level on the silicon film is of order 1200 MPa for devices with ~40% of I-V degradation/enhancement. We attribute the stress phenomenon to the volumetric expansion of field oxide during the LOCOS process View full abstract»

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  • Low contact resistance metallization for gigabit scale DRAM's using fully-dry cleaning by Ar/H2 ECR plasma

    Publication Year: 1997 , Page(s): 588 - 594
    Cited by:  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    A fully-dry cleaning technique with Ar/H2 Electron Cyclotron Resonance (ECR) plasma was developed as a low contact resistance metallization technology for gigabit scale DRAM contacts. By combining with ECR TiN/Ti-CVD, extremely low contact resistances of 296 Ω and 350 Ω for 0.3-μm contact diameter with aspect ratio of 7 were realized on n+ and p+ diffusion layers, respectively. No leakage current was observed. By using this technology, a DRAM ULSI, which was planarized by Chemical Mechanical Polishing (CMP) and had deep contact holes with aspect ratio of 6, was successfully demonstrated View full abstract»

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  • Uniform and high performance of monolithically integrated 1×12 array of planar GaInAs photodiodes

    Publication Year: 1997 , Page(s): 559 - 564
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    In this article, we describe the fabrication of a monolithically integrated 1×12 array of GaInAs/InP planar photodiodes, which has highly uniform characteristics in dark current, capacitance and crosstalk capacitance, quantum efficiency, and the frequency bandwidth at 3-dB reduction with a deviation of ±1%. Besides, each diode on the array exhibits an extremely low dark current of 75 pA, a low capacitance of ~2.3 pF and a crosstalk capacitance between adjacent diodes of ~0.36 pF, a high quantum efficiency of 95% at 1.3 μm and 89% at 1.53 μm, the 3-dB frequency of >2 GHz, and a small 1/f noise component over a wide operating voltage range. Also, the diode on the array has a negligible degradation after the burn-in test of -20 V, 200°C, and 20 h View full abstract»

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  • Hot-carrier degradation of p-MOSFET's under analog operation

    Publication Year: 1997 , Page(s): 607 - 617
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    The hot-carrier degradation of p-MOSFET's is investigated from the viewpoint of analog operation. We apply sensitive measurement methods to determine drain current, drain conductance, and transconductance in the saturation regime besides the commonly investigated parameters in the linear regime of operation. Those investigations are performed for different gate lengths in order to allow comparisons between the shortest channels used for digital and the long channels usually used for analog operation, it is found that the drain conductance important in many analog applications, does not show a channel length dependence for gate lengths above 1.5 times the minimum gate length. The stress time dependencies are determined predominantly finding logarithmic behaviors. These findings are explained by a model which highlights the importance of the lengths of the regions of damage and carrier velocity saturation. Moreover, the dependencies of the different characterization parameters on stress time, channel length and voltages of operation are evaluated. Finally, methods are given for extrapolation of degradation of analog parameters to operating conditions for reliability assurance View full abstract»

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  • Scaled silicon MOSFETs: degradation of the total gate capacitance

    Publication Year: 1997 , Page(s): 584 - 587
    Cited by:  Papers (37)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB)  

    We use a fully quantum-mechanical model to study the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs. We show that, when the device is in weak and moderate inversion, the inclusion of image and many-body exchange-correlation effects increases both the inversion layer and total gate capacitances and shifts the Ns=Ns(VG) characteristics of the device toward lower gate voltages View full abstract»

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  • Simulation of semiconductor devices with non-ideal metallic contacts

    Publication Year: 1997 , Page(s): 679 - 681
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    A comprehensive model of metal-semiconductor contacts that includes both thermionic emission and tunneling effects is reported. The model is particularly suited for the simulation of power devices. As an application example, simulation results of a hybrid Schottky-/pn-diode, also known as Junction Barrier Controlled Schottky Diode (JBS) or Merged pn-Schottky Diode (MPS), are presented View full abstract»

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  • Determination of bit-rate and sensitivity limits of an optimized p-i-n/HBT OEIC receiver using SPICE simulations

    Publication Year: 1997 , Page(s): 551 - 558
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    The sensitivity of an OEIC receiver depends essentially on the physical sources of device and circuit noise referred to its input, provided that the inter-symbol interference (ISI) makes no significant contribution. For well designed receivers, the latter situation can be realized only at an optimum bandwidth (f3 dB.opt) for a given bit rate (B) or vice versa. In this paper, we have determined the relationship between the bit rate and the 3-dB bandwidth for negligible and pre-set levels of ISI for an optimized p-i-n/HBT transimpedance receiver with adjustable bandwidth. We have used SPICE simulations in the frequency domain to determine the effect of device and circuit noise, and SPICE transient analysis to determine the effect of ISI on the sensitivity. The ratio f3 dB.opt/B has been found to vary from 0.65 to 0.45 when B changes from 10 to 20 Gbps for the OEIC receiver used View full abstract»

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  • Area-efficient layout design for CMOS output transistors

    Publication Year: 1997 , Page(s): 635 - 645
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    A novel layout design to effectively reduce the layout area of the thin-oxide NMOS and PMOS devices in CMOS output buffers with ESD consideration is proposed. With respect to the traditional finger-type layout, the large-dimension output NMOS and PMOS devices are realized by multiple octagonal cells. Without using extra ESD-optimization process, the output NMOS and PMOS devices in this octagon-type layout can provide higher driving/sinking current and better ESD robustness within a smaller layout area. The drain-to-bulk parasitic capacitance at the output node is also reduced by this octagon-type layout. Experimental results in a 0.6-μm CMOS process have shown that the output driving (sinking) current of CMOS output buffers in per unit layout area is increased 47.7% (34.3%) by this octagon-type layout. The HBM (MM) ESD robustness of this octagon-type output buffer in per unit layout area is also increased 41.5% (84.6%), as comparing to the traditional finger-type output buffer. This octagon-type layout design makes a substantial contribution to the submicron or deep-submicron CMOS IC's in high-density and high-speed applications View full abstract»

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  • Photon counting III-V hybrid photomultipliers using transmission mode photocathodes

    Publication Year: 1997 , Page(s): 672 - 678
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    This paper reports on the development of solid-state hybrid photomultiplier tubes using high quantum efficiency, transmission mode, III-V photocathodes. The first strike low-noise gain mechanism in these devices is provided via electron bombardment of a solid-state GaAs Schottky diode. In addition, a second-stage gain is provided by solid-state avalanching within a GaAs Schottky APD (SAPD) anode. A combined gain of 2×104, adequate for photon counting, is achieved. Device bandwidth, exceeding 1 GHz, is optimized by tailoring the diode anode structure. The combined traits of this device provide high quantum efficiency, large dynamic range, large bandwidth, and adequate gain for photon counting. Photon counting beyond 1 μm is feasible for a cooled device. The tube structure, diode anode structure, noise issues and preliminary photon counting results are discussed View full abstract»

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  • Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's

    Publication Year: 1997 , Page(s): 627 - 634
    Cited by:  Papers (45)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    The normal and reverse short-channel effect of LDD MOSFET's with lateral channel-engineering (pocket or halo implant) has been investigated. An analytical model is developed which can predict Vth as a function of Leff, VDS, VBS, and pocket parameters down to 0.1-μm channel length. The new model shows that the Vth roll-up component due to pocket implant has an exponential dependence on channel length and is determined roughly by (Np)¼Lp. The validity of the model is verified by both experimental data and two-dimensional (2-D) numerical simulation. On the basis of the model, a methodology to optimize the minimum channel length Lmin is presented. The theoretical optimal pocket implant performance is to achieve an Lmin approximately 55~60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement. The process design window of pocket implant is analyzed. The design tradeoff between the improvement of short-channel immunity and the other device electrical performance is also discussed View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego