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IEEE Transactions on Computers

Issue 1 • Date Jan. 1997

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Displaying Results 1 - 15 of 15
  • 1996 reviewers list

    Publication Year: 1997, Page(s):125 - 128
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    Freely Available from IEEE
  • On dictionary-based fault location in digital logic circuits

    Publication Year: 1997, Page(s):48 - 59
    Cited by:  Papers (27)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    In this work, fault location based on a fault dictionary is considered at the chip level. To justify the use of a precomputed dictionary in terms of computation time, the computational effort invested in computing a dictionary is first analyzed. The number of circuit diagnoses that need to be performed dynamically, without the use of precomputed knowledge, before the overall diagnosis effort excee... View full abstract»

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  • Radix 2 division with over-redundant quotient selection

    Publication Year: 1997, Page(s):85 - 92
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    In this paper we present a new radix 2 division algorithm that uses a recurrence employing simple 3-to-2 digit carry-free adders to perform carry-free addition/subtraction for computing the partial remainders in radix 2 signed-digit form. The quotient digit, during any iteration of the division recursion, is generated from the two most-significant radix 2 digits of the partial remainder and indepe... View full abstract»

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  • Crash resilient communication in dynamic networks

    Publication Year: 1997, Page(s):14 - 26
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    An end-to-end data delivery protocol for dynamic communication networks is presented. The protocol uses bounded sequence numbers and can tolerate both link failures and (intermediate) processor crashes. Previous bounded end-to-end protocols could not tolerate crashes. We present a self-stabilizing version of the algorithm that can recover from crashes of the sender and the receiver as well as of i... View full abstract»

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  • A graph partitioning approach to sequential diagnosis

    Publication Year: 1997, Page(s):39 - 47
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    This paper describes a generalized sequential diagnosis algorithm whose analysis leads to strong diagnosability results for a variety of multiprocessor interconnection topologies. The overall complexity of this algorithm in terms of total testing and syndrome decoding time is linear in the number of edges in the interconnection graph and the total number of iterations of diagnosis and repair neede... View full abstract»

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  • A cellular structure for a versatile Reed-Solomon decoder

    Publication Year: 1997, Page(s):80 - 85
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    A new cellular structure for a versatile Reed-Solomon (RS) decoder is introduced based on time domain decoding algorithm. The time domain decoding algorithm is restructured to be suitable for introducing the cellular structure. The main advantages of this structure are its versatility and very simple cellular structure. By versatile decoder we mean a decoder that can be programmed to decode any (n... View full abstract»

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  • Secure communication with chaotic systems of difference equations

    Publication Year: 1997, Page(s):27 - 38
    Cited by:  Papers (16)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    The paper presents chaotic systems of difference equations that can effectively encrypt information. Two classes of systems are presented: The first one (Class 1) is optimized for secure communications over reliable channels, while the second (Class 2) tolerates transmission noise at the expense of reduced parameter space size. The nonlinearity of these systems is achieved by designing proper piec... View full abstract»

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  • On minimizing the lengths of checking sequences

    Publication Year: 1997, Page(s):93 - 99
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A general model for constructing minimal length checking sequences employing a distinguishing sequence is proposed. The model is based on characteristics of checking sequences and a set of state recognition sequences. Some existing methods are shown to be special cases of the proposed model and are proven to construct checking sequences. The minimality of the resulting checking sequences is discus... View full abstract»

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  • Topologies of combined (2 log N-1)-stage interconnection networks

    Publication Year: 1997, Page(s):118 - 124
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    A combined (2 log N-1)-stage interconnection network (denoted by Δ⊕Δ') is constructed by concatenating two Omega-equivalent networks (Δ and Δ') with the rightmost stage of Δ and the leftmost stage of Δ' overlapped. Benes network and the (2 log N-1)-stage shuffle-exchange network are two examples of such networks. Although these two networks have received i... View full abstract»

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  • Nonprime memory systems and error correction in address translation

    Publication Year: 1997, Page(s):75 - 79
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    Using a prime number p of memory banks on a vector processor allows a conflict-free access for any slice of p consecutive elements of a vector stored with a stride not multiple of p. To reject the use of a prime number of memory banks, it is generally advanced that address computation for such a memory system would require systematic Euclidean division by the number p. The Chinese Remainder Theore... View full abstract»

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  • Selective broadcast data distribution systems

    Publication Year: 1997, Page(s):100 - 104
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    This paper describes a two tier architecture for high speed data distribution. The architecture consists of a database interface network which distributes information from a central database to a number of servers, and a user interface network which distributes information from the servers to the user terminals. The database interface network uses the Selective Broadcast technique to distribute da... View full abstract»

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  • Design and analysis of high performance multistage interconnection networks

    Publication Year: 1997, Page(s):110 - 117
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    Small switching elements are the key components of multistage interconnection networks (MINs) used in multiprocessors and in high speed switching fabrics. Clock design for synchronous MINs is an important issue. The existing models assume that the clock period consists of two parts. The control messages are transferred between switching stages during the first part, and the actual data transfer ta... View full abstract»

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  • DEPEND: a simulation-based environment for system level dependability analysis

    Publication Year: 1997, Page(s):60 - 74
    Cited by:  Papers (76)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    The paper presents the rationale for a functional simulation tool, called DEPEND, which provides an integrated design and fault injection environment for system level dependability analysis. The paper discusses the issues and problems of developing such a tool, and describes how DEPEND tackles them. Techniques developed to simulate realistic fault scenarios, reduce simulation time explosion, and h... View full abstract»

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  • Analysis of dual-link networks for real-time applications

    Publication Year: 1997, Page(s):1 - 13
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Next-generation networks are expected to support a wide variety of services. Some services such as video, voice, and plant control traffic have explicit timing requirements on a per-message basis rather than on the average. In this paper, we develop a general model of dual-link networks to support real-time communication. We examine the desirable properties of this network and the difficulties in ... View full abstract»

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  • A class of error control codes for byte organized memory systems-SbEC-(Sb+S)ED codes

    Publication Year: 1997, Page(s):105 - 109
    Cited by:  Papers (7)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    A new class of error control codes, single byte error correcting and single byte plus single bit error detecting codes, are presented. The codes are suitable for semiconductor memory systems organized in a b-bit-per-chip manner, b⩾2, and more efficient than previously known codes with as strong error control capabilities View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org