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Components, Packaging, and Manufacturing Technology, Part C, IEEE Transactions on

Issue 4 • Date Oct. 1996

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Displaying Results 1 - 14 of 14
  • The Second "Adhesives '96" International Conference

    Page(s): 0_1
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    Freely Available from IEEE
  • 1996 Index IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part C: Manufacturing Vol. 19

    Page(s): 326 - 332
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    Freely Available from IEEE
  • Use of neural networks in modeling relations between exposure energy and pattern dimension in photolithography process [MOS ICs]

    Page(s): 290 - 299
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    The photolithography process is one of the most complex operations in semiconductor production. Exposure energy definition is particularly critical because it strongly affects the operation results. Very complex links exist between exposure energy, pattern critical dimensions, photo resist thickness, and resistivity. At present, the wafer test experimental procedure is used in order to define suitable exposure energy. With the aim of finding a less expensive control criterion of exposure operation in the photolithography process, a neural network has been developed that is able to model the relation between exposure energy and pattern dimensions measured in different positions on the wafer. As a result, the neural network model developed has been found to perform as well as the very expensive test wafer procedure and constitutes a good alternative to this one, allowing for a remarkable cost reduction View full abstract»

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  • Lasersonic bonding of TAB components to epoxy-glass circuit boards

    Page(s): 277 - 282
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    The lasersonic bonding process is an alternative to soldering for the attachment of tape automated bonding (TAB) and other fine-pitch, surface-mounted components to epoxy-glass circuit cards. In this process, a special laser-assisted wire bonder attaches gold-plated TAB component leads to bare copper pads on the card. No solder or flux is required, and leads with very fine widths and spacings can be attached. Bonding is effected by the simultaneous application of heat and ultrasonic energy through a bonding tip held with force against the component lead. Laser energy is transmitted through a fiber optic cable into the hollow tip to supply heat to the bonding tip. Leads are attached one at a time at a speed of 6-8 per second. Details of the equipment used, bonding process conditions, and reliability test results are presented. A thermocouple sensor and feedback control system for the bonding process were designed, and observations regarding the performance of the tip and optical fiber are presented View full abstract»

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  • Surface insulation resistance methodology for today's manufacturing technology

    Page(s): 300 - 306
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    Corrosive contaminants left on a circuit from assembly and manufacturing processes present reliability problems. Contemporary surface insulation resistance (SIR) measurement procedures consist of daily resistance measurements across a comb pattern on samples that age in environmental chambers. Yet these tests lack information on the corrosiveness of the contaminants and often exhibit inconsistency as quantitative measures. A dc continuous measurement method is used here to study the fundamental science behind these measurements for ionic contaminants on a printed circuit board. For ionic contaminants, such as those left from low-solids-fluxes (LSF), the SIR values exhibited continuous and irreversible changes during the test. The dc voltage causes mobile ions to migrate toward the electrodes and thus deplete these ions from the insulating surface. Therefore, only the initial measurement on a virgin sample gives the true quantitative measure of these contaminants. Subsequent rise in SIR value does not indicate an improvement in reliability but rather the presence of mobile ions. Once the board is depleted of ions, reversing the applied voltage polarity cannot restore the initially low SIR value. Instead, it only gives a slow drop followed by a slow rise in the SIR value. These changes are responsible for many measurement anomalies commonly observed under the dc-biasing schemes in existing SIR measurement specifications and standards where the SIR values are recorded only once daily, An alternate SIR measurement using a large ac voltage to monitor product reliability needs be explored. An ac voltage or a small dc voltage causes little net ion migration and therefore gives more consistent results. However a small ac or dc voltage does not produce the desired aging effects of the large dc voltage used in present SIR measurement standards. Preliminary results from the large ac voltage measurements here also gave much slower changes in the measured SIR values. Yet the large ac voltage used may still cause voltage-acceleration of some real-life degradation and failure mechanisms View full abstract»

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  • A robust metric for measuring within-wafer uniformity

    Page(s): 283 - 289
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    Within-wafer uniformity is traditionally measured by the signal-to-noise ratio (SNR), defined as the estimated standard-deviation of within-wafer measurements over the mean of those measurements, Unfortunately, in the presence of deterministic variations of the response over the wafer (such as the bull's eye effect of some processes), the SNR is sensitive to both the location and the number of the measurements taken, A robust metric for describing within-wafer uniformity is developed and compared with the SNR method. The new metric, termed the integration statistic (I) is shown to be robust to both the location and number of measurements taken on the wafer and has lower variance than the SNR metric. The implications of this robust behavior are that fewer measurements can be taken to achieve a given accuracy in the uniformity estimate and that uniformity estimates are consistent with respect to variations in the orientation of the uniformity pattern to the measurement pattern View full abstract»

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  • Assembly of planar array components using anisotropic conducting adhesives-a benchmark study: pt.I. Experiment

    Page(s): 257 - 263
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    This paper presents new results from an experimental and theoretical program to evaluate relevant process parameters in the assembly of a 500 μm pitch area array component using anisotropic conductive adhesive (ACA) materials. This experimental configuration has features of micro ball grid array (μBGA), chip scale packaging (CSP), and also flip-chip and conventional ball grid array (BGA) package structures. A range of materials combinations have been evaluated, including (random filled) adhesive materials based on both thermoplastic and thermosetting resin systems, combined with both organic and thick-film on ceramic substrate materials. The ACAs used have all been applied as films, and hence are also known as anisotropic conducting films (ACF). The test assemblies have been constructed using a specially developed instrumented assembly system which allows the measurement of the process temperatures and pressures and the consequent bondline thickness reduction and conductivity development. The effects of the process parameters on the resulting properties, particularly conductivity and yield, are reported, A complementary paper indicates the results of computational fluid dynamics (CFD) models of the early stages of the assembly process which allow the extrapolation of the present results to finer pitch geometries View full abstract»

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  • FCOB reliability evaluation simulating multiple rework/reflow processes

    Page(s): 270 - 276
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    Flip-chip assembly [direct chip attach (DCA) or flip-chip on board (FCOB)] on printed wiring boards (PWBs), in conjunction with conventional leaded device surface mount technology, is beginning to proliferate in compact and portable systems. DCA with conventional controlled collapse chip connection (C4) bumps requires solder coated bond pads to allow joining in typical surface mount technology (SMT) reflow cycles. A flip-chip device on a typical FCOB/SMT board will usually experience no high temperature excursions after the die joining and underfill encapsulant cure unless the board undergoes a rework cycle. FCOB single chip packages and multichip modules are now in development with standard C4 bumps, and a new Motorola “E-3” bump which requires no solder on bond pads. These solder interconnects must be stable through multiple heat treatments expected in subsequent system level assembly and repair operations. Flip-chip plastic ball grid arrays (FC-PBGAs) will typically undergo three solder reflow, or reheat, cycles to ~220°C subsequent to initial flip-chip reflow assembly. The multiple reheats are for BGA ball attach, board level BGA SMT assembly, second side BGA SMT assembly, and possible rework operations. In this paper, the effect of multiple reheats on the solder connection microstructure and strength (before, and after, underfill encapsulation), and the integrity of the underfill encapsulant adhesive and cohesive strength is reported, using both FCOB single chip packages and multiple chip modules. The effect of multiple reheats on electrical resistance of daisy chain nets, and die stress (radius of curvature), is also reported. Hot air gun rework (before underfill) is simulated and standard belt furnace reflows are utilized. Cross sections of bump connections and underfill interfaces were studied to assess changes induced by the temperature exposures. The reliability of the FCOB assemblies was assessed via temperature cycle, thermal shock, and autoclave tests View full abstract»

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  • Assembly of planar array components using anisotropic conducting adhesives-a benchmark study: II. Theory

    Page(s): 264 - 269
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    For pt.I see ibid., vol.19, no.4, pp.257-63 (1996). This paper presents new results from an experimental and theoretical program to evaluate relevant process parameters in the assembly of a 500 μm pitch area array component using anisotropic conductive adhesive (ACA) materials. This experimental configuration has features of micro ball grid array (μBGA) chip scale packaging (CSP) and also flip-chip and conventional ball grid array (BGA) package structures. The paper presents the results of computational fluid dynamics (CFD) models of the early stages of the assembly process when the adhesive is squeezed out between the device and the substrate. Experimental results on the assembly trials are presented in an accompanying paper and have been previously reported at the Adhesives in Electronics Conference, Gothenburg, 1996. The CFD models outlined here show how those results might be expected to change for smaller pitches View full abstract»

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  • Process induced residual stresses in isotropically conductive adhesive joints

    Page(s): 251 - 256
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    Mechanical and thermomechanical tests were conducted to characterize conductive adhesives in terms of dimensional stability and viscoelastic properties. Dynamic testing results were converted from the frequency domain into the time domain. Those results were then incorporated into the ABAQUS finite element (FE) code, in which a finite element analysis (FEA) was conducted to investigate the stress development and stress relaxation process in the conductive adhesive joints by taking into account the viscoelastic properties of the conductive adhesive. Experimental results showed that the stresses in the conductive adhesive can relax significantly at elevated temperatures. Based on the experimental data and FEA result, a new cure schedule is proposed for the conductive adhesive studied View full abstract»

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  • Run by run control of chemical-mechanical polishing

    Page(s): 307 - 314
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    A prototype hardware/software system has been developed and applied to the control of single wafer chemical-mechanical polishing (CMP) processes. The control methodology consists of experimental design to build response surface and linearized control models of the process, and the use of feedback control to change recipe parameters (machine settings) on a lot by lot basis. Acceptable regression models for a single wafer polishing tool and process were constructed for average removal rate and nonuniformity which are calculated based on film thickness measurement at nine points on 8-in blanket oxide wafers. For control, an exponentially weighted moving average model adaptation strategy was used, coupled to multivariate recipe generation incorporating user weights on the inputs and outputs, bounds on the input ranges, and discrete quantization in the machine settings. We found that this strategy successfully compensated for substantial drift in the uncontrolled tool's removal rate. It was also found that the equipment model generated during the experimental design was surprisingly robust; the same model was effective across more than one CMP tool, and over several months. We believe that the same methodology is applicable to patterned oxide wafers; work is in progress to demonstrate patterned wafer control, to improve the control, communication, and diagnosis components of the system, and to integrate real-time information into the run by run control of the process View full abstract»

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  • Electrically conductive adhesives for surface mount solder replacement

    Page(s): 241 - 250
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    Electrically conductive adhesives offer a lead free, relatively low temperature process for attachment of surface mount components to printed circuit boards (PCB's). The National Center for Manufacturing Sciences (NCMS) Conductive Adhesives project has defined a requirement for an isotropically conductive adhesive (ICA). In this study, 25 commercially available silver-filled epoxies were evaluated for joint resistance stability on copper and tin/lead surface finishes after 500 h of 85°C/85% RH aging. Mechanical properties were evaluated through lap shear and impact testing. This testing led to a set of requirements for a surface mount adhesive including a volume resistivity of 1 mΩ-cm, less than a 20% shift in resistance after aging, and the ability to pass six drops with a plastic leaded chip carrier (PLCC) 44 package from a height of 1.52 m (60 in). Promising candidate adhesives identified in the screening study were evaluated on a circuit board test vehicle with a variety of components. Assembly revealed a narrow processing window when compared to solder. Impact testing demonstrated that current materials have inadequate impact strength for many components and accelerated T/H aging reveals unstable electrical resistance with Sn/Pb finished components. Preliminary data is included on a new adhesive formulation that has been developed to address the shortcomings of currently available ICAs View full abstract»

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  • Effect of polyimide processing on multichip glass ceramic module fabrications

    Page(s): 315 - 325
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    This paper discusses the yield analysis of the thin film wiring layers fabricated on the 127 mm multichip glass ceramic modules (MCM-D), currently used on the IBM Enterprise System/9000 family of computer processors. To select a suitable polyimide (PI) for the thin film wiring layer, modules were fabricated with either the 3,3',4,4'-benzophenone tetracarboxylic dianhydride-1,3-bis(3-aminophenoxy)benzene (BTDA-APB) or the pyromellitic dianhydride-oxydianiline (PMDA-ODA) polyimide. By keeping all other processing parameters and structures the same, the wiring layers fabricated with the PMDA-ODA polyimide exhibited significantly better yield than those made of the BTDA-APB PI. The yield loss in the modules fabricated with the BTDA-APB PI occurred during thermal processing, where some of the transmission lines fabricated atop the PI were found cracked. Further investigations indicate that, during lift-off processing, the presence of a small contaminant, such as a fiber, metal flake, a particle, or polishing scratches can expose the PI to the hot N-methylpyrollidinone (NMP) solvent. Depending on the polyimide used for thin film processing, the diffusion and swelling of the PI by the low molecular weight organic solvent can potentially produce significant damage to the polyimide/Cu wiring structure and the consequent yield loss of the modules due to line opens. The magnitude of the damage was found to depend on the rate of solvent diffusion, process temperature, lift-off time and the amount of PI swelling during processing. To understand these important process parameters in detail, in-plan solvent diffusion and PI swelling in the PMDA-ODA and BTDA-APB films were quantitatively measured. It was found that the rate of in-plane (X-Y plane) solvent diffusion in BTDA-APB is D=0.0617 ×ex-(-9.4 Kcal/RT) cm2/s versus D=0.00155×exp(-10.24 Kcal/RT) cm2/s for the PMDA-ODA film. Both types of PI films were fully imidized at 375°C in nitrogen for 1 h. Thus, the rate of lateral diffusion of NMP in BTDA-APB is approximately 150 times faster than that of the PMDA-ODA film at 85°C. Furthermore, the swelling of PMDA-ODA PI in the 85°C NMP bath is 45% versus 82% for the BTDA-APB PI. The poor elongation property of the BTDA-APB film (strain at break ~4-7% versus 90-130% for the PMDA-ODA PI) further aggravated the solvent problem, BTDA-APB was always found cracked or crazed after being exposed to the NMP solvent, making it very vulnerable to the lift-off process. Consequently, by selecting the PMDA-ODA polyimide for module manufacturing, along with an improved clean room manufacturing facility, the glass ceramic MCM-D has become an extremely reliable product with excellent manufacturing yield View full abstract»

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  • Mechanical failure in COB-technology using glob-top encapsulation

    Page(s): 232 - 240
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    There are several reasons for mechanical stresses in “globbed” assemblies. For example: cure shrinkage; thermal gradients; and moisture diffusion. Thermal mismatch between substrate, silicon die, and encapsulant represent a main reason for thermally induced stresses and is investigated in detail. The filled polymers used have shown temperature, time, and moisture dependent mechanical characteristics. The viscoelastic properties of the encapsulant below the glass transition temperature (Tg) are represented by a Prony series sum of exponentials with three terms, while the temperature dependence is included by a temperature time shift formula. Finite element (FE)-simulations including the creep characteristics allow the evaluation of thermally induced stresses. The calculations show the major stress concentration to occur at the inner edge between die/adhesive/encapsulation and the ceramic board. Local stress concentrations arise at the upper interfacial edge die/encapsulation and at the outer border of the glob-top. Furthermore, the theoretical results are compared with observations of thermally cycled hybrids made by scanning acoustic microscopy (SAM) and metallographic investigations. In this way not only the influence of thermal cycling, but also humidity exposure on the glob-top's integrity was evaluated. The typical failures were shown to be delaminations at the epoxy encapsulant interface View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope