By Topic

Solid-State Circuits, IEEE Journal of

Issue 3 • Date March 1997

Filter Results

Displaying Results 1 - 21 of 21
  • IEEE Solid-State Circuits Society Predoctoral Fellowship Award for 1996-1997

    Publication Year: 1997 , Page(s): 298
    Save to Project icon | Request Permissions | PDF file iconPDF (19 KB)  
    Freely Available from IEEE
  • A 10-b, 100-MS/s CMOS A/D converter

    Publication Year: 1997 , Page(s): 302 - 311
    Cited by:  Papers (51)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1068 KB)  

    A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-μm CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

    Publication Year: 1997 , Page(s): 407 - 418
    Cited by:  Papers (20)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    Several techniques to reduce the ground bounce effect in CMOS chips are described. The effective width of the predrive and final driver of a CMOS output buffer is automatically adjusted to compensate for process, voltage, and temperature (PVT) variations. The slew rate of the predrive nodes is controlled by introducing a digitally weighted capacitance. Finally, a compensated active resistance is inserted into both the power and ground leads to further dampen the oscillations. These techniques allow the buffer to behave uniformly over the entire PVT range. Measurements of a 0.5-μm CMOS test chip have demonstrated that these new buffers generate 2.5× less ground bounce when compared to conventional buffers. An external resistance is required to set a reference current View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range

    Publication Year: 1997 , Page(s): 329 - 336
    Cited by:  Papers (27)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    A 5-V 24-b audio delta-sigma A/D converter has been developed. The single chip integrates stereo delta-sigma modulators, a voltage reference, and a decimation filter. A fourth-order cascaded delta-sigma modulator using a local feedback technique was employed to avoid overload without sacrifice in noise performance. A two-stage decimation filter architecture which reduces digital noise was developed. A new multistage comb filter was used for the first-stage, and a bit-serial finite impulse response (FIR) filter was used for the second stage. The 25.8 mm2 chip was fabricated in 0.7-μm CMOS with low threshold MOS devices. Measured results show 111 dB dynamic range and 103 dB peak signal-to-(noise plus distortion)S/(N+D) View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low noise readout detector circuit for nanoampere sensor applications

    Publication Year: 1997 , Page(s): 337 - 348
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    A readout detector IC has been developed which is capable of detecting nanoampere photo-current signals of interest in a high (microampere) background illumination or dc noise level (SNR=80 dB). The readout detector sensor IC processes transient signals of interest from a separate photo-diode pixel array chip. Low noise signal conditioning, filtering, and signal thresholding implement smart sensor detection of only “active pixels.” This detector circuit can also be used to perform signal conditioning for other sensor applications that require detection of very small signals in a high background noise environment View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integrated circuits for data transmission over twisted-pair channels

    Publication Year: 1997 , Page(s): 398 - 406
    Cited by:  Papers (24)  |  Patents (74)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    This paper discusses typical architectures and challenges in designing integrated circuits for data transmission over twisted-pair wire channels. To highlight the various architectural approaches, two main applications are discussed-high-bit-rate digital subscriber loop (HDSL) and fast-Ethernet. Although these two applications have orders of magnitude difference in their bit rates, they share many common building blocks including line-drivers, 24 wire hybrids, echo cancellation, digital equalization, and clock recovery. Typical integrated circuit approaches for realizing each of these blocks are presented as well as possible tradeoffs. Finally, future challenges facing integrated circuit designers are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The modeling, characterization, and design of monolithic inductors for silicon RF IC's

    Publication Year: 1997 , Page(s): 357 - 369
    Cited by:  Papers (256)  |  Patents (64)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Floating-point datapaths with online built-in self speed test

    Publication Year: 1997 , Page(s): 444 - 449
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1036 KB)  

    This paper describes floating-point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 μm CMOS technology and embedded in a 125 MHz, 291 MFLOPS vector pipelined processor for use in supercomputers. A new online test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which has traditionally been difficult View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1-GHz CMOS up-conversion mixer

    Publication Year: 1997 , Page(s): 370 - 376
    Cited by:  Papers (22)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    A high-frequency linear MOS mixer topology is presented for the implementation of a 1-GHz up-conversion mixer in a standard 0.7-μm CMOS technology. The high output bandwidth has been achieved by the development of an nMOS-only current amplifier that converts the modulated current of the nMOS mixing transistor biased in the linear region to the RF output voltage View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A DSP for DCT-based and wavelet-based video codecs for consumer applications

    Publication Year: 1997 , Page(s): 460 - 467
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    We have developed a video digital signal processor (VDSP1) which performs real-time encoding and decoding for discrete cosine transform- (DCT-) based algorithms such as ITU-T H.261, H.263 and wavelet-based subband encoding algorithms. This LSI is suitable for consumer applications, as it was implemented using 0.5 μm CMOS process technology to realize compactness (one million transistors on 65 mm2) and low power (maximum: 560 mW). It features a processing unit which performs wavelet filtering at high speeds, a compact DCT circuit, and a fast, flexible DRAM interface for low-cost systems. At 40 MHz, a single chip is capable of processing quarter common intermediate format (QCIF) (176×144 pixels) size pictures at a rate greater than 15 frames/s View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Capacitive coupling and quantized feedback applied to conventional CMOS technology

    Publication Year: 1997 , Page(s): 419 - 427
    Cited by:  Papers (24)  |  Patents (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    An on-chip capacitor is formed under the bond pad to block the DC level of input signals. Capacitively coupled signals suffer the “zero wander” effect which causes the local DC level on the second plate of the capacitor to be dependent on the bit activity rate. A quantized feedback technique using a self-triggered decision circuit is used to reestablish local DC voltage levels in the receiver and eliminates the “zero wander” effect. The input signals can be detected over a large common mode range independent of the bit activity rate and over a large frequency range. Silicon area and power dissipation are reduced since encoding and decoding of the bit stream is not required. The circuit has been implemented in silicon using a conventional digital 0.5 μm CMOS technology. This receiver can detect a 231-1 pseudorandom pattern at 800 Mb/s with no errors and can operate down to a data rate of 2 kHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A mixed-signal decision-feedback equalizer that uses a look-ahead architecture

    Publication Year: 1997 , Page(s): 450 - 459
    Cited by:  Papers (15)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    A mixed-signal decision-feedback equalizer (DFE) that uses a look-ahead architecture is described. The parallelism in the look-ahead DFE (LA DFE) achieves an increase in the data rate over a conventional DFE with a small increase in area. Fully differential analog circuits perform the convolution operation in the LA DFE, and the coefficient adaption is carried out by digital circuits. The LA DFE occupies 23 mm 2 in a 2-μm CMOS process and operates at 50 Mb/s while dissipating 260 mW View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by local feedback loops

    Publication Year: 1997 , Page(s): 321 - 328
    Cited by:  Papers (16)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    The design of a low-power, low-voltage, 12-b 8-kHz bandwidth ΣΔ modulator for high-quality voice that consumes only 0.34 mW at 1.95 V supply is described. The modulator employs a special architecture in which a third-order modulator is stabilized by a local feedback loop around each integrator. Unlike multistage ΣΔ modulators, this architecture is very tolerant to the modest dc gain of low voltage op-amps. The architecture, together with special circuit techniques, permits a low-voltage switched capacitor implementation at 1.95 V-3.3 V supply using standard 1.2-μm CMOS technology View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A partitioning scheme for optimizing interconnect power

    Publication Year: 1997 , Page(s): 433 - 443
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    An architecture-synthesis technique for the low-power implementation of real-time applications is presented. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. This results in reduced usage of long high-capacitance buses, fewer accesses to multiplexors and buffers, and more compact layouts. Experimental results show average reductions in bus and multiplexor power of 57.8 and 56.0%, respectively, resulting in an average reduction of 25.8% in total power. In addition, we analyze the effect of varying levels of partitioning on power consumption and present models for estimating bus capacitance View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A BiCMOS programmable continuous-time filter using image-parameter method synthesis and voltage-companding technique

    Publication Year: 1997 , Page(s): 377 - 387
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB)  

    This paper presents a BiCMOS realization of a structure-programmable continuous-time filter built with sections synthesized by the image-parameter method and demonstrating the feasibility of the voltage companding technique. The circuit implements any one of four lowpass filters of order 2-5 or one fourth-order bandpass filter by interconnecting a set of identical cells. The filter is obtained by a component level substitution transforming a gm -C structure into its log-domain equivalent. The gm-C structures are derived from LC ladder prototypes which are synthesized using the image-parameter method. This technique can be extended to realize higher order filters using multichip configurations. As an example, six lowpass filters (order 6-11) and three bandpass filters (order 6, 8, and 10) have been measured using three chips. The programmable filters can additionally be frequency tuned from 10-100 kHz with a low total harmonic distortion (THD) despite their class AB operation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A highly linear CMOS Gm-C bandpass filter with on-chip frequency tuning

    Publication Year: 1997 , Page(s): 388 - 397
    Cited by:  Papers (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (596 KB)  

    A fourteenth-order CMOS transconductance-C (Gm-C) bandpass filter with on-chip automatic frequency tuning is described. By using highly linear Gm-C integrators, the filter achieves 75 dB dynamic range over 700 kHz noise bandwidth. The measured intermodulation distortion (IM3) @ 600 kHz for a 4 Vpp input signal is only -61 dB. On-chip automatic frequency tuning provides more than 300% center frequency range (i.e., 165-505 kHz) of the filter with ±1% frequency accuracy. The 0.7-μm CMOS filter measures 4.8 mm 2 and consumes 70 mW from a single 5 V power supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Structured design of a 288-tap FIR filter by optimized partial product tree compression

    Publication Year: 1997 , Page(s): 468 - 476
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    A compact 10-b, 288-tap finite impulse response (FIR) filter is designed by adopting structured architecture that employs an optimized partial product tree compression method. The new scheme is based on the addition of equally weighted partial products resulted from 288 multiplications of the filter coefficients and the inputs. The 288 multiplication and 287 addition operations are decomposed to add 1440 partial products and the sign extension operations are manipulated independently to ensure the operation at 72 MHz, the internal clock frequency generated by the integrated phase-locked loop (PLL) clock multiplier. In addition to the optimized transmission gate full adder, modified carry save compression circuits such as 4:2 and 5:5:2 compressors are used to perform decomposed partial product addition. This structured approach enables cascade design that requires more than 288-tap FIR filtering. The completed 288-tap FIR fitter core occupies 5.36×7.29 mm2 of silicon area that consists of 371732 transistors in 0.6-μm triple-metal CMOS technology, and it consumes only 0.8 W of average power at 3.3 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers

    Publication Year: 1997 , Page(s): 312 - 320
    Cited by:  Papers (104)  |  Patents (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    A parallel-pipelined A/D converter with an area and power efficient architecture is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-b pipeline is realized using just three amplifiers (instead of seven amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a 52 Msamples/s prototype A/D converter that is Intended for a switched digital video application has been implemented in a 0.9-μm CMOS technology. The device occupies 15 mm 2 and dissipates 250 mW from a 5 V supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low voltage SRAM for embedded applications

    Publication Year: 1997 , Page(s): 428 - 432
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 μW. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 μW. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Converters dedicated to long-term monitoring of strain gauge transducers

    Publication Year: 1997 , Page(s): 349 - 356
    Cited by:  Papers (12)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    This paper presents two new strain gauge bridge-to-pulse position modulation (PPM) converters. They have been developed in 2-μm BiCMOS technology. The first one uses a chopper amplifier and a voltage-to-time converter associated in a feedback loop. This topology mainly exhibits an automatic offset cancellation capability, a ratiometric transfer function, and 10-b accuracy. The second one is a voltage-to-frequency converter using the switched-capacitor (SC) technique. It is an optimized version in terms of size minimization and noise rejection. Furthermore, a special RF transmitter has been designed in order to send the data from an intracorporal sensing and conditioning circuitry to an external computer dedicated to data analysis. Moreover, these converters are insensitive to offset drifts and are well suited for long term monitoring of orthopedic implants used for the treatment of bone fractures View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's

    Publication Year: 1997 , Page(s): 477 - 482
    Cited by:  Papers (3)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    Recently, as multimedia large scale integrated devices (LSIs) have developed, there has been strongly increased demand for high-speed/high-bandwidth LSIs which integrate the DRAM core and logic elements (CPU etc.). However, the high-speed/high-bandwidth operation induces the large switching noise. This noise degrades the DRAM's operating margin, and especially its data retention characteristics. In this paper, we analyze the noise transmission model and propose DRAM and logic compatible design methodologies to maintain the reliability of high-speed/high-bandwidth system LSIs. We also show that good experimental results are obtained on the test device. Furthermore, we propose the most suitable VDD/GND line scheme for on-chip DRAM system LSI View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan