# IEE Proceedings - Computers and Digital Techniques

## Filter Results

Displaying Results 1 - 15 of 15
• ### GRMIN2: A heuristic simplification algorithm for generalised Reed-Muller expressions

Publication Year: 1996, Page(s):376 - 384
Cited by:  Papers (4)  |  Patents (3)
| |PDF (976 KB)

Branches are a major limiting factor to instruction-level parallelism. One solution is to execute several branches simultaneously using multiway branching architectures. Such architectures are especially important when the instruction issue width becomes large. The authors study the problem of compile-time scheduling of branch operations on such architectures: an optimisation called branch merging... View full abstract»

• ### Optimum partitioning of rectilinear layouts

Publication Year: 1996, Page(s):440 - 442
Cited by:  Papers (1)
| |PDF (372 KB)

Given a set S of nonoverlapping axis-parallel rectangles placed inside a rectangular region B, a partition of the space B/S is called a free space partition'. A simple proof of a formula on the number of rectangles in a minimum free space partition is presented. Based on this formula, it is shown that a minimum free space partition can be computed using a well known geometric graph search algorit... View full abstract»

• ### Alternative algorithm for optimisation of Reed-Muller universal logic module networks

Publication Year: 1996, Page(s):385 - 390
Cited by:  Papers (1)
| |PDF (584 KB)

Reed-Muller universal logic modules (RM-ULMs) can be used as individual modules or as networks to implement RM functions of any number of variables. For a large RM expansion, it is generally more efficient to realise it using cascades of low-order RM-ULMs. A programmed algorithm for the optimisation of the number of modules at the sub-system level has already been published. In the paper an altern... View full abstract»

• ### Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filters

Publication Year: 1996, Page(s):436 - 439
Cited by:  Papers (7)
| |PDF (300 KB)

Recurrence relations and fully pipelined novel cell-level systolic architectures are suggested for massively parallel implementation of two-dimensional FIR and linear phase FIR filters. Owing to the higher level of parallelism, the proposed structures would yield more throughput over the existing structures. Besides, it can be flexibly configured according to the throughput requirement of the appl... View full abstract»

• ### New program model for program partitioning on NUMA multiprocessor systems

Publication Year: 1996, Page(s):431 - 435
| |PDF (512 KB)

A new program model is presented to accurately represent parallel programs for partitioning and scheduling problems. This model extends the graphic representation of the macrodataflow by considering the complex communication options supported by NUMA systems. The proposed model shows not only task precedence relations but also data sharing status. Moreover, a new partitioning method based on the p... View full abstract»

• ### Removing CSC violations in asynchronous circuits by delay padding

Publication Year: 1996, Page(s):413 - 420
| |PDF (936 KB)

A novel alternative for removing CSC (complete state coding) violations in asynchronous circuit synthesis for STGs (signal transition graphs) is presented. The main feature of the work is to exploit delays in the physical circuit to remove CSC violations. Its main advantages are that it: does not need to obey the noninput constraint: and saves area overhead when a CSC violation in the state graph ... View full abstract»

• ### Three-valued quasi-linear transformation for logic synthesis

Publication Year: 1996, Page(s):391 - 400
Cited by:  Papers (3)
| |PDF (984 KB)

A nonlinear transformation, called the sign transform, is defined and studied. It maps all the ternary functions onto themselves, is uniquely invertible and is inherently related to Walsh and Walsh Galois transforms. Decomposable Boolean functions and ternary product terms are mapped analytically into the sign domain. It is shown that sign coefficients describe the structure of a ternary output lo... View full abstract»

• ### Layout-driven chaining of scan flip-flops

Publication Year: 1996, Page(s):421 - 425
Cited by:  Papers (9)
| |PDF (524 KB)

In an era of submicron technology, routing is becoming a dominant factor in area, timing and power consumption. The problem of scan flip-flops chaining with the objective of achieving minimum routing area overhead is studied. The first attempt is to chain the flip-flops at the logic level. To make more accurate decisions on chaining flip-flops, the second attempt is to perform the chaining of scan... View full abstract»

• ### XMESH interconnection network for massively parallel computers

Publication Year: 1996, Page(s):401 - 406
Cited by:  Papers (1)
| |PDF (508 KB)

An XMESH is proposed as a suitable interconnection network for massively parallel computers, and the performance of the proposed interconnection network is analysed. The XMESH has the same horizontal links as those of the toroidal mesh (TMESH); however, it has diagonally crossed links instead of vertical links. The proposed XMESH shows desirable characteristics as an interconnection network for ma... View full abstract»

• ### Difference clocks: a new scheme for logical time in distributed systems

Publication Year: 1996, Page(s):426 - 430
| |PDF (536 KB)

Logical clocks and vector clocks were proposed in the past to capture causality between events of different processes of a distributed computation. However, these clocks could not capture intraprocess concurrency. Later, bit-matrix clocks and hierarchical clocks were developed to capture interprocess concurrency as well as intraprocess concurrency. The major disadvantages of these clocks are the a... View full abstract»

• ### Gaussian-elimination-based algorithm for solving linear equations on mesh-connected processors

Publication Year: 1996, Page(s):407 - 412
| |PDF (560 KB)

The problem of solving a system of N linear equations on a mesh-connected multiprocessor structure is considered. The solution to the problem is obtained by using a Gaussian-elimination-based algorithm called successive Gaussian elimination'. The new algorithm does not contain a separate backsubstitution phase. A two-dimensional array of N×(N+1) processors is employed to obtain the solution... View full abstract»

• ### Exact minimisation of Kronecker expressions for symmetric functions

Publication Year: 1996, Page(s):349 - 354
Cited by:  Papers (1)
| |PDF (604 KB)

In the paper, an algorithm for the exact minimisation of Kronecker expressions (KROs) for totally symmetric functions is presented. KROs are a class of AND/EXOR forms closely related to ordered Kronecker functional decision diagrams (OKFDDs). This close relation is used to obtain a polynomial time minimisation algorithm. A generalisation to partially symmetric functions is investigated. Experiment... View full abstract»

• ### Reliability levels for fault-tolerant linear processing using real number error correction

Publication Year: 1996, Page(s):355 - 363
Cited by:  Papers (1)
| |PDF (1000 KB)

Fault-tolerant linear processing systems using real number codes, as in algorithm-based fault tolerance methodologies, can be extended to include error correction for correcting intermittent errors in the processed output data. The reliability function for a protected system containing correction is considered under simple but realistic assumptions on the arrival of failures in both the normal pro... View full abstract»

• ### Genetic algorithm for variable ordering of OBDDs

Publication Year: 1996, Page(s):364 - 368
Cited by:  Papers (22)  |  Patents (1)
| |PDF (576 KB)

A genetic algorithm (GA) is applied to find a variable ordering that minimises the size of ordered binary decision diagrams (OBDDs). OBDDs are a data structure for representation and manipulation of Boolean functions often applied in CAD. The choice of the variable ordering largely influences the size of the OBDD (i.e. its size may vary from polynomial to exponential in the number of variables). D... View full abstract»

• ### Branch merging for scheduling concurrent executions of branch operations

Publication Year: 1996, Page(s):369 - 375
| |PDF (708 KB)

Branches are a major limiting factor to instruction-level parallelism. One solution is to execute several branches simultaneously using multiway branching architectures. Such architectures are especially important when the instruction issue width becomes large. The authors study the problem of compile-time scheduling of branch operations on such architectures: an optimisation called branch merging... View full abstract»

## Aims & Scope

Published from 1994-2006, IEE Proceedings - Computers and Digital Techniques contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

Full Aims & Scope