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Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Issue 1 • Date Feb 1997

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Displaying Results 1 - 13 of 13
  • Effect of intermetallic compounds on the thermal fatigue of surface mount solder joints

    Publication Year: 1997 , Page(s): 87 - 93
    Cited by:  Papers (48)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    The effect of Cu-Sn intermetallic compounds (IMC) on the fatigue failure of solder joints during thermal cycling has been studied. The samples consist of components [leadless ceramic chip carrier (LCCC)] soldered onto FR-4 printed circuit board (PCB), and are prepared by conventional reflow soldering using a 63Sn-37Pb solder paste. The specimens are subjected to thermal cycling between -35°C and 125°C with a frequency of two cycles per hour until failure. The results indicate that the fatigue lifetime of the solder joints depends on the thickness of IMC's layer between Cu-pad and bulk solder, and the relation of the lifetime to the thickness can be described as a monotonically decreasing curve. The lifetime is very sensitive to the thickness of the IMC when the thickness is less than 1.4 μm. During thermal cycling the thickness of the IMC layer increases and then the interface between IMC and solder becomes gradually flatter. The results of X-ray diffraction and scanning electron microscope (SEM) analysis show that cracks propagate along the interface between the IMC layer and the solder joint. The Cu3Sn (ε-phase) is also found to form between the Cu-pad and η-phase during thermal cycling. On the basis of the above results, the thick and flattened IMC layer is shown to responsible for the fatigue failure of solder joint during thermal cycling. The results of this paper can be used to optimize the reflow soldering process for the fabrication of robust solder joints View full abstract»

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  • Improved heat sinking for laser-diode arrays using microchannels in CVD diamond

    Publication Year: 1997 , Page(s): 104 - 109
    Cited by:  Papers (12)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    This work proposes a novel cooling system for high-power laser-diode arrays, for which the maximum optical output power density per unit surface area is limited by the temperature rise due to self-heating. The proposed system uses a microchannel heat sink made of chemical-vapor-deposited (CVD) diamond, whose high thermal conductivity increases the efficiency of the channel-wall fins and reduces the array-to-coolant thermal resistance using a simple model for the combined conduction and convection problem. The resistance is calculated to be 75% less than that for a conventional configuration using a silicon microchannel heat sink. The present analysis strongly motivates a future experimental study View full abstract»

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  • Thermal limits of flip chip package-experimentally validated, CFD supported case studies

    Publication Year: 1997 , Page(s): 94 - 103
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    This study projects the thermal performance limits of a flip chip package. A plastic, pin grid array (PGA) package with direct chip attach (DCA) interconnect was chosen for the demonstration purpose. The same methodology as developed here can be applied to other flip chip packages, The design rules chosen are the allowable power dissipation for constraints of junction temperature (⩽105°C) and board temperature (⩽90°C) under either free air or forced air (1.27 m/s) condition. An experimentally validated computational fluid dynamics (CFD) model was used to predict the thermal performance limits of the flip chip package. Simulations were run by increasing the power to the package under consideration until either the junction temperature or the board temperature reached its limit. Based on these constraints, the allowable power dissipation in the package was determined to be between 1.7 and 6.7 W in free air and between 2.1 and 13.7 W in 1.27 m/s of air. The validated CFD models offer enormous potential to quickly assess thermal limits of many future flip chip packages and their variations View full abstract»

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  • Return path inductance in measurements of package inductance matrixes

    Publication Year: 1997 , Page(s): 50 - 55
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    Circuit theory is applied to derive a transformation to move the reference in a partial inductance matrix from one lead to another. A package is experimentally characterized with three very different return paths to produce radically different partial inductance matrixes. These matrixes are re-normalized and shown to be equal except for the initial measurement return path. Additional measurements show that repeatability is not affected by the choice of measurement return path. Bandwidth can be affected by the measurement return path View full abstract»

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  • Electrical characteristics of high-performance pin-in-socket and pad-on-pad connectors

    Publication Year: 1997 , Page(s): 64 - 77
    Cited by:  Papers (7)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    Two types of high-performance, high-density connectors, pin-in-socket, and pad-on-pad, are investigated for providing many hundreds of signal contacts in large-panel, card-to-board applications. The two examples were selected as top-of-the-line contenders for mechanically robust interconnections that can be used for transmitting 500 Mb/s and even 1 Gb/s data-rate signals, and with comparable cost. While the pinned connector offers a proven technology, the newly introduced pad-on-pad connector can provide at least 1.5 times higher number of signal contacts and lower crosstalk. Experimental characterization of signal integrity, connector delay, impedance discontinuity, crosstalk, and maximum current capability, is performed for both connectors in order to compare their relative performance View full abstract»

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  • Implementation of a gallium arsenide multichip digital circuit operating at 500-1000 MHz clock rates using a Si/Cu/SiO2 MCM-D technology

    Publication Year: 1997 , Page(s): 17 - 26
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    Two different deposited multichip modules (MCMs) were fabricated in nCHIP's nC3000 Si/Cu/SiO2 process. The first of these MCMs was a passive test coupon containing a variety of microstrip and stripline transmission line structures, allowing the measurement of dc and ac signal amplitude losses in long conductors, as well as assessments of crosstalk and reflections as functions of line dimensions and spacings. The second MCM incorporated sixteen Gallium Arsenide (GaAs) integrated circuits, all designed to work together at clock rates in the hundreds of MHz; all components were attached, face up, with an aluminum wire bonding process. The design, fabrication, assembly and test processes for these modules will be described, as well as the lessons learned about this MCM process for the design of subsystems up to the high hundreds of MHz clock rates View full abstract»

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  • FDTD analysis of the electrical performance for interconnection lines in multichip module (MCM) with perforated reference planes

    Publication Year: 1997 , Page(s): 34 - 41
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    A finite difference time domain (FDTD) approach is demonstrated for analysis of the electrical performance of interconnection lines and the extraction of their equivalent circuit parameters in a multichip-module (MCM) with perforated reference planes. By making an equivalence between uniform and nonuniform interconnection lines and an equivalence between nonuniform interconnection lines and actual physical interconnection lines' structure, the equivalent distributed circuit parameters and transmission characteristic parameters can be obtained from the fields calculated by the FDTD method. The results are compared with those obtained by other methods. The dispersive characteristics of such interconnection lines with perforated reference planes and the coupling between interconnection lines on different layers is also studied in this paper View full abstract»

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  • Package clock distribution design optimization for high-speed and low-power VLSIs

    Publication Year: 1997 , Page(s): 56 - 63
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    With continually increased difficulties of the clock distribution in high speed microprocessors and application-specific integrated circuits (ASICs), the package clock distribution shows very promising advantages. The concurrent design of chip and package will provide the optimal design of a clock network by taking the advantages of package layers. The package layers provide 1000 times less wire resistance and 10 times less wire capacitance than those of interconnects on chip. Therefore, it is more beneficial to route the global clock network on package. The implementation issues of the package clock distribution are described in this paper, including the electrostatic discharge (ESD) circuit design for local clock buffers and transmission line noise suppression for package clock trees View full abstract»

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  • Reliability of the laminate from advanced COPNA-resin/E-glass fabrics system

    Publication Year: 1997 , Page(s): 78 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    Reliability of the advanced COPNA-resin laminate which exhibited high glass transition temperature (Tg) at 255°C, low coefficient of thermal expansion (CTE) at 5-7 ppm (xy-axis) and at 29 ppm (x-axis) was evaluated by temperature-humidity-bias (THB) test, pressure-cooker (PC) test, heat-shock test, heat-cycle test, and conductive anodic filaments (CAF) test. The laminate exhibited higher reliability than the FR-4 graded epoxy-resin laminate in every test, and exhibited higher reliability than the bismaleimide-triazine resin laminate in the THB test, heat-shock test, and heat-cycle test. The high reliability of the advanced COPNA-resin system is considered to be due to its high Tg and small CTE. In this paper, low CTEs of the advanced COPNA-resin laminate are also theoretically studied by using a model for uni-axially reinforced composites View full abstract»

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  • A novel test technique for MCM substrates

    Publication Year: 1997 , Page(s): 2 - 12
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    This paper describes a novel and low-cost test technique that is capable of detecting process related defects such as opens and shorts in multichip module (MCM) substrates. This method is an alternative to existing test methods such as electron beam, capacitance, resistance, and electrical module test (EMT) techniques which are either expensive in terms of test equipment, are cumbersome due to the requirement of multiple probes, have low throughput or provide poor defect coverage. The proposed test method applies a stimulus through a resonator at only one end of the interconnect using a single-ended probe. By measuring the attenuation of the test stimulus due to pole movement relative to known attenuation measurements, interconnect faults such as near-opens, near-shorts, opens, and shorts can be detected. The total test time is projected to be similar to a capacitance method and the hardware cost of test equipment is low. This paper discusses the theoretical details, simulation results, resolution, implementation, and validation of the technique View full abstract»

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  • Multichip MMIC package for X and Ka bands

    Publication Year: 1997 , Page(s): 27 - 33
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    A new multichip monolithic microwave integrated circuit (MMIC) package operable to X and Ka bands has been developed and tested. This package provides space for mounting up to five MMIC chips and has three radio frequency (RF) and five dc feed-throughs. The RF feed-throughs are of a mixed-mode, conductor-backed coplanar waveguide design that minimizes reflections and insertion loss over a wide bandwidth. The dc feed-throughs permit bias access for up to five chips and internal mounting of chip bypass capacitors. Prototypes of the package have been built and tested using miniature coplanar probes. Test results indicate that the RF feed-throughs meet design goals to about 30 GHz and can be used to about 35 GHz. The package has been analyzed using a “Composite Model” approach in which individual elements are separately analyzed and modeled and then combined in a circuit simulator to provide a complete package model. This approach has provided quite good agreement with measured data View full abstract»

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  • Integration of vapor deposited polyimide into a multichip module packaging process

    Publication Year: 1997 , Page(s): 13 - 16
    Cited by:  Papers (5)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB)  

    We report the first full integration of a vapor-deposited polyimide dielectric into a multichip module (MCM) electronic packaging scheme. A robust high-throughput vapor deposition polymerization (VDP) of polyimide has been developed for an interconnection scheme in which thin film metal interconnects are patterned from the top of bare die, down the sides, and onto the substrate circuit board surface. VDP polyimides films have been extensively characterized using infrared spectroscopy and prism coupling techniques. The chemical and electrical properties of the VDP polyimide films are similar to commercially available spin cast polyimides View full abstract»

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  • Modeling and experimental verification of the interconnected mesh power system (IMPS) MCM topology

    Publication Year: 1997 , Page(s): 42 - 49
    Cited by:  Papers (7)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    A new low-cost multichip module (MCM) topology, the interconnected mesh power system (IMPS), has been shown capable of reducing the metal layers of a conventional four-layer MCM by half. To provide a complete MCM on only two metal layers, the IMPS topology provides a unique and complex power distribution system and signal transmission environment. This paper reports on models of the IMPS structure based on finite-difference/partial-inductance methods and PSpice simulation. The models can easily he constructed using a commercial three-dimensional (3-D) field solver and the circuit models can be solved by PSpice. The agreement between the modeled and measured results is excellent. Discrepancies between models and results are also discussed View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope