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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb 1997

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Displaying Results 1 - 18 of 18
  • An Extended Kalman filtering-based method of processing reflectometry data for fast in-situ etch rate measurements

    Page(s): 42 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    In this paper a new algorithm is presented for determining etch rate from single or multiple wavelength reflectometry data. This algorithm is based on techniques from recursive nonlinear estimation theory-Extended Kalman Filtering. A major advantage of our algorithm is extremely high speed, with computation time less than 1 ms on a Pentium PC. Consequently, it can be used in real-time feedback control applications. The speed advantage also makes it a suitable candidate for full wafer (or multi-point) high-speed etch rate measurement View full abstract»

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  • Integrated real-time and run-to-run control of etch depth in reactive ion etching

    Page(s): 121 - 130
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    Reactive Ion Etching (RIE) is a common process step in semiconductor manufacturing, yet the underlying mechanisms remain poorly understood. Our goal is to reduce the variance of etch characteristics by integrating real-time and run-to-run control of plasma and process variables. The run to run controller suggests plasma variable set-points based on the wafer characteristics of the previous run. The real-time controller maintains the suggested plasma variables by manipulating the process inputs during the etch. We have demonstrated the integrated control architecture for rejecting oxygen and loading disturbances in an Applied 8300 Hexode Reactor during a polysilicon etch View full abstract»

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  • Manufacturing improvement team programs in the semiconductor industry

    Page(s): 1 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    Increasing numbers of semiconductor manufacturers are implementing improvement programs at their manufacturing sites (fabs). Yet despite their rising popularity, little attention has focused on the impact of a program's design on its overall effectiveness. This research examines the improvement programs established at ten fabs. A categorization scheme classifies programs according to their use of one of three types of teams: continuous improvement teams (CITs), quality circles (QCs), and self-directed work teams (SDWTs). Results from 188 operator surveys and over 150 interviews with fab employees (including managers, engineers, technicians, supervisors, operators, and representatives from human resources and quality departments) indicate that a number of programs suffer from weak implementation and disorganized management. The failure to carefully design and implement a program is reflected in employee perceptions of the program's effectiveness. Perceptions of CIT programs are found to be significantly lower than those of QC or SDWT programs, both of which feature higher degrees of autonomy and training. Results also highlight a nearly universal failure to integrate production team programs with engineering and maintenance functions. To help improve future programs, design implications and aspects of effective team programs are noted. Special attention is paid to program selection, goal design, organizational support, engineering integration, information systems, and empowerment semantics View full abstract»

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  • Spatial characterization of wafer state using principal component analysis of optical emission spectra in plasma etch

    Page(s): 52 - 61
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    Optical emission spectroscopy (OES) is often used to obtain in-situ estimates of process parameters and conditions in plasma etch processes. Two barriers must be overcome to enable the use of such information for real-time process diagnosis and control. The first barrier is the large number of measurements in wide-spectrum scans, which hinders real-time processing. The second barrier is the need to understand and estimate not only process conditions, but also what is happening on the surface of wafer, particularly the spatial uniformity of the etch. This paper presents a diagnostic method that utilizes multivariable OES data collected during plasma etch to estimate spatial asymmetries in commercially available reactor technology. Key elements of this method are: first, the use of principal component analysis (PCA) for dimensionality reduction, and second, regression and function approximation to correlate observed spatial wafer information (i.e., line width reduction) with these reduced measurements. Here we compare principal component regression (PCR), partial least squares (PLS), and principal components combined with multilayer perceptron neural networks (PCA/MLP) for this in-situ estimation of spatial uniformity. This approach has been verified for a 0.35-μm aluminum etch process using a Lam 9600 TCP etcher. Models of metal line width reduction across the wafer are constructed and compared: the root mean square prediction errors on a test set withheld from training are 0.0134 μm for PCR, 0.014 μm for PLS, and 0.016 μm for PCA/MLP. These results demonstrate that in-situ spatially resolved OES in conjunction with principal component analysis and linear or nonlinear function approximation can be effective in predicting important product characteristics across the wafer View full abstract»

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  • PIER: an early treatment of inter-process interactions

    Page(s): 112 - 120
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    The period of maximum profitability in semiconductor products is short and occurs early in production, thereby forcing the industry to continually strive to reduce the development time for new process flows. Described in this paper is the Process Integration Engineers' Resource (PIER), currently being developed at Stanford University, which is intended to assist the process integration engineer in the specification of process targets and the timely completion of process integration. The approach taken by this software tool is based on an early analysis of inter-process interactions and aids in the scheduling of process module development. The tool is employed prior to complete target specification, and a qualitative simulation of the skeletal process flow is used to identify all modeled inter-process interactions for an arbitrary flow. Predefined interaction models and the simulated wafer conditions enable this interaction identification. A semantic network representing the critical dependencies between processes resulting from the Identified interactions is then constructed. An understanding of the interactions and process dependencies is expected to improve the development of the flow in four ways: (1) potential flow design errors are more easily identified before process target specification; (2) more complete information is provided to the unit process engineers; (3) ramifications of subsequent process changes are identified; and (4) a partially ordered graph of processes allows for improved process sequences for the flow's target specification and development View full abstract»

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  • Modeling the effect of hot lots in semiconductor manufacturing systems

    Page(s): 185 - 188
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    The presence of hot lots or high-priority jobs in semiconductor manufacturing systems is known to significantly affect the cycle time and throughput of the regular lots since the hot lots get priority at all stages of processing. In this paper, we present an efficient analytical model based on re-entrant lines and use an efficient, approximate analysis methodology for this model in order to predict the performance of a semiconductor manufacturing line in the presence of hot lots. The proposed method explicitly models scheduling policies and can be used for rapid performance analysis. Using the analytical method and also simulation, we analyze two re-entrant lines, including a full-scale model of a wafer fab, under various buffer priority scheduling policies. The numerical results show the severe effects hot lots can have on the performance characteristics of regular lots View full abstract»

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  • A novel method for sub-micron particle detection in clean liquids

    Page(s): 11 - 16
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    A novel approach to the detection of liquid-borne submicrometer particles (extendible to ultra-clean liquids) is described. The key concept is to coax the submicrometer particles to soft cavitate and then detect the ensuing transient bubble activity acoustically rather than the particle itself (which has only a weak scattering signature). The method, therefore, relies on facilitating acoustic microcavitation through acoustic coaxing. Acoustic microcavitation is brought about by low megahertz acoustic fields giving rise to micrometer-size bubbles that live a few microseconds. Liquid-borne microparticles do not, ordinarily, cause any cavitation when exposed to strong sound fields (of 1 MHz). If, however, a very weak, high-frequency auxiliary acoustic field (e.g., 30 MHz) is added to this sound field, cavitation by the microparticles is readily facilitated. This technique of facilitating cavitation is referred to as “acoustic coaxing”. Results of preliminary experiments indicate that even smooth spherical microparticles can be coaxed to cause cavitation. An explanation of the “acoustic coaxing effect” is offered. The physics seems not to be limited by the smallness of microparticles (effect possible up to 50 nm). This novel method based on acoustic coaxing of microcavitation promises to be a good basis for on-line, real time monitoring of liquid-borne submicronic particulates. This method is not limited to small sensing volumes and, unlike optical methods, it has an intrinsic, location specific, signal enhancement at the source particle View full abstract»

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  • Molecular dynamics analysis of reflow process of sputtered aluminum films

    Page(s): 131 - 136
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    It is important that aluminum films fill the grooves on silicon substrates if high-density devices are to be produced. In this paper, we calculate the changes in the free-surface profiles of deposited aluminum films in a high-temperature reflow process on flat and grooved substrates using a molecular dynamics simulation. We use an atomic-scale model to analyze the micron-scale flow on the substrates. The relationships between droplet formation and the parameters of initial film-thickness distribution, aluminum film temperature, and bond energy between the aluminum and substrate atoms are also investigated. When the film at the bottom of the groove walls is thick, film breaks are observed at the top of the groove walls and a large volume of the film flows into the bottom of the groove. We also calculate the change in the aluminum-film profiles for a high-temperature sputtering deposition process View full abstract»

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  • Closed-loop measurement of equipment efficiency and equipment capacity

    Page(s): 84 - 97
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    Formal definitions for the components of efficiency and capacity, mathematical formulas for computing overall efficiency, and data collection strategies are proposed for rigorous measurement of equipment efficiency and equipment capacity. Measurement of overall equipment efficiency (OEE) under the TPM paradigm is extended to support the maintenance of capacity parameters for production planning. The weaknesses or equipment analyzes based on utilization and aggregate UPH (units per hour) figures are contrasted against the robustness of the proposed approach. Applications in semiconductor factories are discussed View full abstract»

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  • A framework for robust run by run control with lot delayed measurements

    Page(s): 75 - 83
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    This paper considers the run by run control problem. We develop a framework to solve such a problem in a robust fashion. The framework also encompasses the case when the system is subject to delayed measurements. Recent results available for the control of such systems are reviewed, and two examples are presented. The first example is based on the end-pointing problem for a deposition process, and is subject to noise which has both Gaussian and uniform components. The second one is concerned with rate control in an LPCVD reactor View full abstract»

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  • Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

    Page(s): 154 - 166
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    In this work, the effects of plasma-parameter variations on the charging damage of polysilicon-gate MOS capacitor test structures exposed to O2 electron-cyclotron-resonance (ECR) plasmas are investigated. The results show that charging damage is generated when large potential differences exist across the gate-oxide layers of the MOS capacitor test structures and that these potential differences can only occur in the presence of plasma nonuniformities. These results demonstrate the critical need for plasma uniformity during processing, in particular as device dimensions shrink and gate-oxide thicknesses decrease. The plasma parameters were varied by adjusting the neutral gas pressure and by independently biasing a circular grid and a ring electrode located above the wafer. The damage induced in the test wafers during the plasma exposure was characterized with ramp-voltage breakdown measurements. Radial profiles of the floating potential measured with a Langmuir probe were found to vary nonuniformly when the grid electrode was positively biased due to preferential depletion of electrons relative to ions beneath the grid electrode. An equivalent-circuit model of the test wafer and the wafer-stage electrode predicts that the silicon substrate acquires a potential equal to the average of the wafer surface potential. Comparisons of the calculated profiles of the potential difference across the gate-oxide layers of the test structures and whole-wafer maps of the breakdown-voltage measurements show that the majority of the damage occurs where the oxide potential difference is largest and that the damage only occurs in the presence of plasma nonuniformities View full abstract»

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  • Exploiting structure in fast aerial image computation for integrated circuit patterns

    Page(s): 62 - 74
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    Modeling aerial images has recently become a crucial component of semiconductor manufacturing. As all steppers employ partially coherent illumination, such modeling has been computationally intensive for all but elementary patterns. In this paper we describe a fast computational method for calculating aerial images of integrated circuit masks produced by a partially coherent optical projection system. The method described relies on two tools to realize fast computation: (1) coherent decompositions of partially coherent imaging system models as proposed by Pati and Kailath (1994), and (2) the use of “basis” (or building block) images that are well-suited to describe integrated circuit patterns. Examples are presented in which aerial images are computed for large mask areas. The proposed method represents a speed improvement of several orders of magnitude over a more traditional, and more general, approach (SPLAT from the University of California, Berkeley) View full abstract»

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  • Analysis and decomposition of spatial variation in integrated circuit processes and devices

    Page(s): 24 - 41
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    Variation is a key concern in semiconductor manufacturing and is manifest in several forms. Spatial variation across each wafer results from equipment or process limitations, and variation within each die may be exacerbated further by complex pattern dependencies. Spatial variation information is important not only for process optimization and control, but also for design of circuits that are robust to such variation. Systematic and random components of the variation must be identified, and models relating the spatial variation to specific process and pattern causes are needed. In this work, extraction and modeling methods are described for wafer-level, die-level, and wafer-die interaction contributions to spatial variation. Wafer-level estimation methods include filtering, spline, and regression based approaches. Die-level (or intra-die) variation can be extracted using spatial Fourier transform methods; important issues include spectral interpolation and sampling requirements. Finally, the interaction between wafer- and die-level effects is important to fully capture and separate systematic versus random variation; spline- and frequency-based methods are proposed for this modeling. Together, these provide an effective collection of methods to identify and model spatial variation for future use in process control to reduce systematic variation, and in process/device design to produce more robust circuits View full abstract»

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  • Real-time multivariable control of PECVD silicon nitride film properties

    Page(s): 137 - 146
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    This paper reports on the application of quadrupole mass spectrometry (QMS) sensing to real-time multivariable control of film properties in a plasma-enhanced CVD silicon nitride process. Process variables believed to be most important to film deposition are defined (i.e., disilane pressure, triaminosilane pressure, and dc bias voltage) and their responses to system inputs are modeled experimentally. Then, a real-time controller uses this information to manipulate the process variables and hence film performance in real time during film deposition. The relationships between gas concentrations and film performance are shown explicitly where the controller was used to drive the concentrations to constant setpoints. Also, an experiment investigating the effects of an out-of-calibration mass flow controller demonstrates the compensating ability of the real-time controller. The results indicate that in situ sensor-based control using quadrupole mass spectrometry can significantly assist in optimizing film properties, reducing drift during a run, reducing run-to-run drift, creating a better understanding of the process, and making the system tolerant to disturbances View full abstract»

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  • Limited yield estimation for visual defect sources

    Page(s): 17 - 23
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    Although kill rate, kill ratio, and limited yield for visual defects are useful concepts in yield management, the formal definitions of these concepts, how to estimate them, especially in the presence of inspection error, and assumptions necessary for their application, are lacking in the literature. The concept of limited yield as the effect of a visual defect source on overall yield of a process is formally derived and the product of the individual limited yields for the visual defect sources is shown to equal the overall yield of the process. As a result of a more rigorous definition of limited yield, a major simplification in the calculation of limited yield over other methods is obtained. Basic to the notion of limited yield are the concepts of kill rate and kill ratio. The kill rate expresses how likely it is that a die with a certain visual defect will be rejected at probe. The kill ratio is shown to be the increased chance, relative to the baseline yield, of a die being rejected when a particular visual defect type is present. The limited yield concept is discussed and illustrated with a practical example using semiconductor visual defect data View full abstract»

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  • Limitation of the TiN/Ti layer formed by the rapid thermal heat treatment of pure Ti films in an NH3 ambient in fabrication of submicrometer CMOS flash EPROM IC's

    Page(s): 147 - 153
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    In this study, the technical feasibility and limitation of the TiN film formed by the rapid thermal heat treatment (RTHT) in an ammonia ambient for the fabrication of 0.85-μm CMOS flash electrically programmable read only memory (EPROM) integrated circuits having a contact aspect ratio of approximately 1.5, were investigated. When the as-deposited thickness of the Ti film was less than 130 Å, all memory contacts exhibited an “electrically open” contact signature (>4750 Ω/contact). Transmission electron microscopy (TEM) cross section examination of a failed contact chain structure indicated that the failure mechanism could be a physical separation at the W-plug/silicon interface. For the Ti films with thickness between 130 and 240 Å, the contact resistance dropped to a value between 59 and 68 Ω/contact. Furthermore, the contact failure rate (contacts exhibiting “electrically open” signature) decreased as the thickness of the Ti film increased. In this case, the failure mechanism appeared to be the direct contact between the TiN layer and the silicon at the contact interface. This condition was created during the multistep nitridation process where approximately 240 to 250 Å of the Ti film was converted to TiN. For the memory devices having Ti films thicker than 240 Å, all memory contacts were electrically and mechanically stable, and exhibited equivalent or higher circuit yields compared to devices having a sputter deposited TiN/Ti bilayer film (control group) View full abstract»

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  • Cost and cycle time performance of fabs based on integrated single-wafer processing

    Page(s): 98 - 111
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    Visions of future wafer fabs include the use of integrated single-wafer processors to achieve fast cycle times and contain rising production costs. A survey of IC manufacturers, equipment vendors, and IC manufacturing literature was used to generate hypothetical conventional and alternative fabs to evaluate the effect of integrated single-wafer processing on cycle time and cost performance. The distinguishing features of the alternative fab are: (1) all thermal processes performed on single-wafer processors; (2) back-end net cleans performed on single-wafer processors; (3) integration of single-wafer processors into clusters or cells wherever practical, and (4) extensive use of in situ process monitors to replace in-line process monitors. Modeling and simulation of the resulting fabs suggest that integrated single-wafer processing can reduce the cycle time of conventional fabs by about 50% without having a significant effect on wafer production test. Tool integration and single-wafer processing must be used together to achieve these performance improvements. Although traditional lot sizes appeared to be appropriate for both fabs, improvements in cluster tool reliability and process step similarity could change optimal integrated tool configurations and reduce optimal lot sizes in the future View full abstract»

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  • An overview of level set methods for etching, deposition, and lithography development

    Page(s): 167 - 184
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    The range of surface evolution problems in etching, deposition, and lithography development offers significant challenge for numerical methods in front tracking. Level set methods for evolving interfaces are specifically designed for profiles which can develop sharp corners, change topology, and undergo orders of magnitude changes in speed. They are based on solving a Hamilton-Jacobi type equation for a level set function, using techniques borrowed from hyperbolic conservation laws. Over the past few years, a body of level set methods have been developed with application to microfabrication problems. In this paper, we give an overview of these techniques, describe the implementation in etching, deposition, and lithography simulations, and present a collection of fast level set methods, each aimed at a particular application. In the case of photoresist development and isotropic etching/deposition, the fast marching level set method, introduced by Sethian (1996), can track the three-dimensional photoresist process through a 200×200×200 rate function grid in under 55 s on a Sparc10. In the case of more complex etching and deposition, the narrow band level set method, introduced in Adalsteinsson and Sethian (1995), can be used to handle problems in which the speed of the interface delicately depends on the orientation of the interface versus an incoming beam, the effects of visibility, surface tension, reflection and re-emission, and complex three-dimensional effects. Our applications include photoresist development, etching/deposition problems under the effects of masking, visibility, complex flux integrations over sources, nonconvex sputter deposition problems, and simultaneous deposition and etch phenomena View full abstract»

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The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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