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Solid-State Circuits, IEEE Journal of

Issue 1 • Date Jan 1997

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Displaying Results 1 - 20 of 20
  • BiCMOS adjustable linear current mirror

    Page(s): 130 - 134
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB)  

    Two novel BiCMOS adjustable gain linear current mirrors are presented. Variable gain is achieved by introducing a DC voltage into the control loop. Simulation and experimental results indicate that the gain is linear over several decades of signal current. The circuits are designed for maximum voltage swing with cascoded output to provide high output resistance View full abstract»

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  • Multiphase sine-shaper circuit

    Page(s): 126 - 129
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    This paper describes a method of generating multiple sine waves of the same frequency but at different phases. The circuit, relying upon bipolar transistors, is compact and easily produces several phases. The amplitude and the frequency of the sine waves can vary while keeping the phase angle between the different waves constant. A four phase circuit was built on a linear integrated circuit array using bipolar transistors. A similar circuit, also built on the same array, provided temperature compensation. The integrated circuit provided three sine waves to control an induction motor. The phase differences between the three output phases were less than one degree, and amplitude differences were within two percent View full abstract»

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  • A 200 MHz register-based wave-pipelined 64 M synchronous DRAM

    Page(s): 92 - 99
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    A new register-based wave-pipelined scheme for synchronous DRAMs (SDRAMs) is proposed. In this scheme, (N-1) registers are located between a read data bus line pair and a data output buffer and (N-1) read data are stored in parallel in these registers, where N denotes the CAS latency. Since the column data path is not divided and the read data is transmitted directly to the registers, the burst read operation can easily be achieved at a higher operation frequency without a large area penalty or degradation of an internal timing margin. Measured results show that the 64 M SDRAM based on the register-based wave-pipelined scheme can operate up to 200 MHz View full abstract»

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  • A transimpedance CMOS multichannel amplifier with a 50 Ω-wide output range buffer for high counting rate applications

    Page(s): 135 - 138
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    A fast transimpedance multichannel amplifier has been designed, fabricated in CMOS 1.2-μm technology and tested. Each channel consists of a current sensitive preamplifier followed by a voltage amplification stage and an on-chip buffer able to drive 50 Ω loads with an output range of ±800 mV. Measured peaking time at the output is 40 ns and the circuit recovers to baseline in 90 ns. This results in a counting capability of more than 107 hits/s, Signals of both polarities can be handled. The first two stages consume a total of 2 mW per channel and the 50 Ω buffer consumes another 17 mW. The equivalent noise charge (ENC) is 1100 e- rms with a slope of 40e-/pF. The IC is intended for use in gas and solid-state detectors with high particle rate and extensive charge release as in high energy calorimetry View full abstract»

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  • A DC-DC converter for short-channel CMOS technologies

    Page(s): 111 - 113
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    An integrated DC-DC converter with two passive external components was designed and fabricated in an advanced, short-channel (Leff <0.2 μm, Vdd<2 V) CMOS technology. This design was undertaken to examine the feasibility of implementing an inductive buck converter with passive components small enough to fit entirely within a packaged chip. High switching frequencies (>10 MHz) were used to minimize the size of external components, and novel circuits were used to reduce the stress on the short channel devices. Measured efficiencies for a 3.3 V to 1.65 V converter were approximately 75% for output currents from 15 to 40 mA View full abstract»

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  • Delta-sigma modulators using frequency-modulated intermediate values

    Page(s): 13 - 22
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    This paper describes a new first- and second-order delta-sigma modulator concept where the first integrator is extracted and implemented by a frequency modulator with the modulating signal as the input. The result is a simple delta-sigma modulator with no need for digital-to-analog converters, allowing straightforward multibit quantization. Without the frequency modulator, the circuit becomes a frequency-to-digital converter with delta-sigma noise shaping. An experimental first- and second-order modulator has been implemented in a 1.2-μm standard digital CMOS process and the results confirm the theory. For the first-order modulator an input signal amplitude of 150 mV resulted in a signal-to-quantization noise ratio (SQNR) of ≈115 dB at 2 MHz sampling frequency and signal bandwidth of 500 Hz View full abstract»

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  • 20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

    Page(s): 31 - 37
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    An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s View full abstract»

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  • A novel power-off mode for a battery-backup DRAM

    Page(s): 86 - 91
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    This paper proposes a new DRAM power-off mode, in which the power source is completely shut off during the standby cycle, resulting in a zero standby leakage current. By introducing a new word-line power-off/on sequence and a grounded cell plate technique, all cell data are maintained after power source is turned off and on. Although the proposed mode requires a power-on current, an average standby leakage current is reduced by a factor of 1000, and the total standby current including both the leakage current and refresh current is reduced by a factor of 10 in a 1 Gb DRAM. The proposed circuit technique was verified by a 64 Kb DRAM test chip. All cell data were successfully maintained after the power source switching. The measured power-off time was as long as the measured data retention time in the conventional DRAM standby mode View full abstract»

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  • Program load adaptive voltage generator for flash memories

    Page(s): 100 - 104
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    This paper describes a program load voltage generator for flash memories. It is based on an adaptive feedback loop which senses the current delivered to the memory cells during programming and adjusts the output voltage accordingly to compensate for the voltage drop caused by the programming current across the bit-line select transistors. The proposed circuit (silicon area=0.065 mm2) was integrated in a 0.8-μm CMOS 4 Mb flash memory device (0.6 μm in the matrix). Experimental evaluations showed that very effective compensation is achieved, with bit-line voltage kept at the desired value during the whole programming operation. A spread as small as 70 mV was measured between the single-bit and 16-b programming cases View full abstract»

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  • New single-clock CMOS latches and flipflops with improved speed and power savings

    Page(s): 62 - 69
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    New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits View full abstract»

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  • A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design

    Page(s): 114 - 118
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    This paper proposes a new pipelined full-adder circuit structure for the implementation of pipelined arithmetic modules. With both static and dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio. The adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduce the latency. The MAC is fabricated in a 0.8-μm single-poly-double-metal CMOS process. The post-layout simulation shows that the pipelined 1-b full adder can work up to 350 MHz with a 3 V power supply. The whole MAC chip that contains 4200 transistors is measured to operate a 125 MHz using 3.3 V power supply View full abstract»

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  • An eight-bit prefetch circuit for high-bandwidth DRAM's

    Page(s): 105 - 110
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    A low-power and area-efficient data path circuit for high-bandwidth DRAMs is described. For fast burst read operations, eight data per data I/O are stored in local latches placed close to sense amplifiers. As implemented in a 16-Mb synchronous DRAM (SDRAM), this 8-b prefetch circuit allows an early precharge command and a fast access time because it provides low-capacitance data lines for segmented bit-line pairs. At a column address strobe (CAS) latency of two and a burst length of four, the SDRAM demonstrates 100-MHz seamless read operations from different row addresses, because the row precharge and read access latencies are hidden during the burst cycles. The layout of the prefetch circuit is not limited by the bit-line pitch, and data path circuits are connected by a second-metal layer over the memory cells. As a result, a small chip size of 99.98 mm2 is attained. Low-capacitance data lines and small local latches result in low active power. In a 100-MHz full-page burst mode, the SDRAM with a 1 M×16-b configuration dissipates 60 mA at 3.6 V View full abstract»

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  • Six-terminal MOSFET's: modeling and applications in highly linear, electronically tunable resistors

    Page(s): 4 - 12
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    The electrical properties of a six-terminal MOSFET are studied and a strong-inversion model is derived. Due to its special structure, the six-terminal MOSFET can be operated as a highly-linear, electronically-tunable resistor. This is managed by applying proper voltages at the terminals of the structure, achieving channel uniformity independent of applied signals. Measurements on fabricated test devices yield distortion levels of -90 dB for 1 Vp-p signals View full abstract»

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  • A differential built-in current sensor design for high-speed IDDQ testing

    Page(s): 122 - 125
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    A new built-in current sensor design for IDDQ testing is presented in this paper. Our design overcomes performance limitations encountered by previous sensors by using a novel differential architecture which allows early and accurate detection of abnormal quiescent current following the switching transient. This differential design also naturally compensates for inaccuracies due to any build up of leakage currents and subthreshold conduction effects when relatively large circuit partitions are tested. A test circuit utilizing the sensor in a built-in self-test environment has been fabricated. At clock speeds of up to 31.25 MHz the sensor accurately detects all six of the defects that were implanted in the test chip. SPICE3 simulations of the circuit indicate that with careful design, this sensor can accurately detect faults at operational speeds in a variety of situations View full abstract»

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  • A capacitive sensing integrated circuit for detection of micromotor critical angles

    Page(s): 23 - 30
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    The theory, design, and measured performance of an integrated circuit which enables closed-loop control of electrostatic micromotors is presented. The micromotor control integrated circuit (MCIC) consists of low-noise sense electronics designed to detect critical rotor angles to a resolution of 0.5° (0.05 fF) at a 1-MHz sampling rate, and control logic which cycles the micromotor drive state during continuous rotation to maintain maximum torque, independent of loading. Noise due to MOSFET switches and amplifiers in the analog section is modeled and shown to be 32 μV referred to the system input, i.e., about half the desired switching resolution. The MCIC was fabricated using a 2-μm, n-well CMOS process and functions as expected. The noise probability density function was measured using MCIC's digital output for different values of input-to-ground capacitance in order to verify the noise model. Good agreement with theory was observed, although the comparator exhibited some offset and hysteresis View full abstract»

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  • Analysis and prevention of DRAM latch-up during power-on

    Page(s): 79 - 85
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    The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period View full abstract»

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  • A 0.25-μm CMOS 0.9-V 100-MHz DSP core

    Page(s): 52 - 61
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    This paper describes a 0.25-μm CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-μm CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs View full abstract»

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  • A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI

    Page(s): 119 - 121
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous View full abstract»

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  • Low-voltage dynamic BiCMOS CLA circuit with carry skip using novel full-swing logic

    Page(s): 70 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1612 KB)  

    This paper presents novel low-voltage dynamic BiCMOS logic gates and an improved carry look-ahead (CLA) circuit with carry skip using these new dynamic BiCMOS topologies. The well-known “MOS clock feedthrough effect” is used to achieve full swing with substantially reduced low-to-high evaluation delay in the logic gates, thus, resulting in reduced carry propagation/bypass delay in the cascaded CLA array. Simulations at clocking frequency of 100 MHz, using 2-μm BiCMOS process parameters and supply voltage in the range of 2-4 V displays lower gate delay and lower power dissipation compared to other recent dynamic BiCMOS logic topologies. The circuit has no dc power dissipation, race, or charge redistribution problems. An 8-b CLA with 5-b carry skip was achieved in 2.917 ns. This speed is significantly higher than other recent dynamic BiCMOS CLA designs. In addition, the new CLA circuit is more compact compared to previous dynamic BiCMOS CLA designs. A tiny chip was fabricated using the MOSIS Orbit Analog 2-μm V-well CMOS process for the experimental verification of the new low-voltage dynamic BiCMOS topologies View full abstract»

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  • A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs

    Page(s): 38 - 51
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    A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan