Issue 12 • Date Dec. 1996
Filter Results
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A Parallel Multipole Accelerated 3-D Capacitance Simulator Based on an Improved Model
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PDF (264 KB)
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Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping"
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PDF (94 KB)
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Bit-parallel multidelay simulation
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PDF (196 KB)
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Balanced partitioning
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PDF (244 KB)
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Enhanced multipole acceleration technique for the solution of large Poisson computations
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PDF (184 KB)
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Automatic state space decomposition for approximate FSM traversal based on circuit analysis
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PDF (372 KB)
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Aims & Scope
Contains articles on methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities.
Meet Our Editors
Editor-in-Chief
Sachin Sapatnekar
University of Minnesota
Dept. of Electrical and Computer Engineering
4-174 Keller Hall, 200 Union Street SE
Minneapolis, MN 55455 55455 USA
sachin@umn.edu


