By Topic

IEEE Design & Test of Computers

Issue 4 • Date Winter 1996

Filter Results

Displaying Results 1 - 9 of 9
  • IEEE Design & Test of Computers - 1996 Annual Index, Volume 13

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (558 KB)
    Freely Available from IEEE
  • FPGA architectural research: a survey

    Publication Year: 1996, Page(s):9 - 15
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    A recent article by S. Brown and J. Rose (see ibid., vol.13, no.2, p.42-57, 1996) summarized the classes of field programmable devices currently available and described many of the most important commercial devices. We describe current research studies, evaluating the enhancements to FPGA architecture each recommends and how these architectures affect the two most important metrics: total chip are... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Minimizing FPGA interconnect delays

    Publication Year: 1996, Page(s):16 - 23
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    Optimizing FPGA routing architectures for speed performance also involves improving the CAD tools for mapping circuits. We provide a detailed example of how to design FPGA architectures by examining several important issues associated with interconnect resources for FPGAs that use SRAM programming technology. Our experiments examine two important metrics: the speed performance of implemented circu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A fault injection technique for VHDL behavioral-level models

    Publication Year: 1996, Page(s):24 - 33
    Cited by:  Papers (78)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1628 KB)

    Designers are realizing the advantages of performing fault injection early, using simulation to inject faults into a model of the design rather than the actual system. The authors describe their technique for injecting faults into a system's VHDL behavioral level model. To demonstrate the technique, they evaluate an embedded control system providing fail safe operation in the railway industry View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Transmission coefficient correction for DACs

    Publication Year: 1996, Page(s):34 - 39
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    Many digital-to-analog converters achieved as integrated circuits by CMOS and bipolar technologies have a transmission coefficient error, often called full scale error. The article presents circuits to correct for such error in DACs with resistive ladder network R/2R and separate resistor, r View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • BIST for D/A and A/D converters

    Publication Year: 1996, Page(s):40 - 49
    Cited by:  Papers (28)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    The expense of specialized equipment can be a problem in testing high resolution D/A converters. A BIST alternative that tests offset voltage, integral nonlinearity, differential nonlinearity, and gain error without such equipment or the use of a digital signal processor or microcontroller shows promise. We also extend the same technique to test a wide range of A/D converters View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Circular self-test path for FSMs

    Publication Year: 1996, Page(s):50 - 60
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1540 KB)

    Circular self test path (CSTP) is an attractive method for automatically transforming sequential circuits generated by automatic synthesis tools into BIST structures. The authors extend this method-making it more suitable for FSMs derived from synthesized control parts-and are integrating it into an industrial design flow supporting testable synthesis. The CSTP approach provides good results in te... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IDDQ testing: issues present and future

    Publication Year: 1996, Page(s):61 - 65
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB)

    IDDQ testing has emerged from a company specific CMOS IC test technology in the 1960s and 1970s to become a worldwide accepted technique that is a requirement for low defective parts per million levels and failure rates. It is the single most sensitive test method to detect CMOS IC defects, and an abundance of studies have laid a solid foundation for why this is so. The IDDQ ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • How ATE planning affects LSI manufacturing cost

    Publication Year: 1996, Page(s):66 - 73
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    To analyze the effects of automatic test equipment planning on total LSI manufacturing cost cost per chip, we simulate manufacturing cost by combining discrete event simulation and detailed parametric models of the LSI manufacturing system. This combination provides a more realistic evaluation than previous methods. For our example of ATE planning, we optimize the distribution of LSI testers betwe... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty