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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 4 • Date Dec. 1996

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Displaying Results 1 - 9 of 9
  • VLSI implementation of discrete wavelet transform

    Publication Year: 1996, Page(s):421 - 433
    Cited by:  Papers (81)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1367 KB)

    This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is simple, modular, and cascadable for computation of one or multidimensional DWT. It comprises of four basic units: input delay, filter, register bank, and control unit. The proposed architecture is systolic in nature and performs both high- and low-pass coefficient calculations with only one set of mu... View full abstract»

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  • Performance-driven MCM partitioning through an adaptive genetic algorithm

    Publication Year: 1996, Page(s):434 - 444
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1207 KB)

    We present a novel genetic algorithm-based partitioning scheme for multichip modules (MCM's) which integrates four performance constraints simultaneously: pin count, area, heat dissipation, and timing. We also present a similar partitioning algorithm based on evolutionary programming. Experimental studies demonstrate the superiority of these methods over deterministic Fiduccia-Mattheyes (FM) algor... View full abstract»

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  • Efficient arithmetic using self-timing

    Publication Year: 1996, Page(s):445 - 454
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1043 KB)

    Recent advances in VLSI technology have facilitated high levels of integration and the implementation of faster circuits on a chip. Most of the improvements in the performance of digital systems have been brought about by such faster technologies. However, these improvements in technology have brought along with them a host of other constraints. In the faster deep submicron technologies, the wire ... View full abstract»

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  • A 3.5 in 230 Mbytes read-channel chip set for magneto-optical disk drives

    Publication Year: 1996, Page(s):455 - 463
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (988 KB)

    A read-channel chip set for rewritable 3.5 in 230 Mbytes magneto-optical disk drives (MOD) is presented. The front-end chip includes an automatic gain control (AGC) circuit, a programmable six-pole two-zero equiripple filter/equalizer, a DC restore circuit, and pulse detectors. The back-end contains a frequency synthesizer phase-locked loop (PLL) and a data separator PLL with 3:1 operating range t... View full abstract»

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  • ATM switching architectures for wafer-scale integration

    Publication Year: 1996, Page(s):464 - 471
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    This paper proposes the use of wafer-scale integration (WSI) technology for ATM switching systems and presents two different switching architectures specifically designed for WSI. WSI is particularly useful for switching networks since the interconnection lengths are minimized when the entire network is laid out on a single semiconductor wafer. We propose a defect-tolerant multipath buffered cross... View full abstract»

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  • CMOS design of the tree arbiter element

    Publication Year: 1996, Page(s):472 - 476
    Cited by:  Papers (20)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (462 KB)

    An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact d... View full abstract»

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  • Moment models of general transmission lines with application to interconnect analysis and optimization

    Publication Year: 1996, Page(s):477 - 494
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1551 KB)

    In this paper, we present new moment models for uniform, nonuniform and coupled transmission lines. The moment model of a line is based on the relationships between the two port currents (KCL) and the two port voltages (KVL) of the line. The parameters of the model depend on the mean values of the voltage moments and the weighted voltage moments of the line. Simple formulas are given to compute th... View full abstract»

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  • Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (61 KB)

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  • 1996 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 4

    Publication Year: 1996, Page(s):498 - 505
    Request permission for commercial reuse | PDF file iconPDF (874 KB)
    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu