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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 4 • Date Dec. 1996

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Displaying Results 1 - 9 of 9
  • VLSI implementation of discrete wavelet transform

    Page(s): 421 - 433
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1367 KB)  

    This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is simple, modular, and cascadable for computation of one or multidimensional DWT. It comprises of four basic units: input delay, filter, register bank, and control unit. The proposed architecture is systolic in nature and performs both high- and low-pass coefficient calculations with only one set of multipliers. In addition, it requires a small on-chip interface circuitry for interconnection to a standard communication bus. A detailed analysis of the effect of finite precision of data and wavelet filter coefficients on the accuracy of the DWT coefficients is presented. The architecture has been simulated in VLSI and has a hardware utilization efficiency of 87.5%. Being systolic in nature, the architecture can compute DWT at a data rate of N/spl times/10/sup 6/ samples/s corresponding to a clock speed of N MHz. View full abstract»

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  • Performance-driven MCM partitioning through an adaptive genetic algorithm

    Page(s): 434 - 444
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    We present a novel genetic algorithm-based partitioning scheme for multichip modules (MCM's) which integrates four performance constraints simultaneously: pin count, area, heat dissipation, and timing. We also present a similar partitioning algorithm based on evolutionary programming. Experimental studies demonstrate the superiority of these methods over deterministic Fiduccia-Mattheyes (FM) algorithm and simulated annealing (SA) technique. Our approach performs better than another genetic algorithm-based method recently reported. The adaptive change of crossover and mutation probabilities results in better convergence of the partitioning algorithm. View full abstract»

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  • Efficient arithmetic using self-timing

    Page(s): 445 - 454
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1043 KB)  

    Recent advances in VLSI technology have facilitated high levels of integration and the implementation of faster circuits on a chip. Most of the improvements in the performance of digital systems have been brought about by such faster technologies. However, these improvements in technology have brought along with them a host of other constraints. In the faster deep submicron technologies, the wire delays constitute a significant portion of the overall delay of the system and hence some of the advantages of faster technologies are lost. The high level of integration necessitates clock distribution schemes which minimize skew across the die. These result in area penalties and adversely affect the level of integration possible at the chip level. Hence, changes in the basic architecture of computing elements of a system, which when implemented in silicon introduces reduced interconnect delays and simpler clock distribution networks, will result in more effective performance improvements. The work presented here examines the implementation of the most basic element in any datapath-an adder. The adder, a carry elimination adder (CEA), uses self-timing at both the algorithmic and implementation levels and presents a minimal hardware high speed addition mechanism. The adder exploits the nature of the input operands dynamically, which results in its average case convergence time approaching that of the ubiquitous carry lookahead adder (CLA) and the hardware complexity of a carry ripple adder (CRA). Use of self-timing results in the elimination of a global clock and hence clock-skew. View full abstract»

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  • A 3.5 in 230 Mbytes read-channel chip set for magneto-optical disk drives

    Page(s): 455 - 463
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    A read-channel chip set for rewritable 3.5 in 230 Mbytes magneto-optical disk drives (MOD) is presented. The front-end chip includes an automatic gain control (AGC) circuit, a programmable six-pole two-zero equiripple filter/equalizer, a DC restore circuit, and pulse detectors. The back-end contains a frequency synthesizer phase-locked loop (PLL) and a data separator PLL with 3:1 operating range to support a constant density recording with 8-24 Mb/s data rate (or code rate of 16 to 48 Mb/s) in (2, 7) run-length limited (RLL) encoding format. The architecture of the chip provides high degree of programmability through a serial microprocessor interface, fast switching (<1 /spl mu/s) between sector mark and data detector modes, and four levels of power management in a 1.5 /spl mu/m 4 GHz BiCMOS process. With a nominal power supply of 5 V, the chip set dissipates 600 mW during normal operation and 1 mW during sleep mode. View full abstract»

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  • ATM switching architectures for wafer-scale integration

    Page(s): 464 - 471
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    This paper proposes the use of wafer-scale integration (WSI) technology for ATM switching systems and presents two different switching architectures specifically designed for WSI. WSI is particularly useful for switching networks since the interconnection lengths are minimized when the entire network is laid out on a single semiconductor wafer. We propose a defect-tolerant multipath buffered crossbar (MBC) with an expandable structure which can easily be scaled up or down according to the choice of wafer size. We also design an ATM-based Manhattan-street network (MSN) as an alternative architecture, suitable for wafer-scale implementation. We compare the two architectures from different standpoints such as performance, defect-tolerance, delay, practicality, testability, complexity, yield, and area. View full abstract»

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  • CMOS design of the tree arbiter element

    Page(s): 472 - 476
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (462 KB)  

    An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact design for the tree arbiter element which offers eager forward-propagation of requests. It compares favorably with a well-known design in which request propagation must wait for arbitration to complete. Our analysis and simulations also suggest that no performance improvement will be obtained by incorporating eager acknowledgment of releases. All of the designs considered in this paper are speed-independent, a formal property of a network of elements which can be taken as a positive indication of their robustness. View full abstract»

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  • Moment models of general transmission lines with application to interconnect analysis and optimization

    Page(s): 477 - 494
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    In this paper, we present new moment models for uniform, nonuniform and coupled transmission lines. The moment model of a line is based on the relationships between the two port currents (KCL) and the two port voltages (KVL) of the line. The parameters of the model depend on the mean values of the voltage moments and the weighted voltage moments of the line. Simple formulas are given to compute these mean values efficiently. By using such models and moment matching techniques, interconnects modeled as transmission line networks can be efficiently simulated. In addition, by using moment sensitivities, we demonstrate that wire sizing optimization can be carried out for layout design. View full abstract»

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  • 1996 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 4

    Page(s): 498 - 505
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    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Yehea Ismail
CND Director
American University of Cairo and Zewail City of Science and Technology
New Cairo, Egypt
y.ismail@aucegypt.edu