By Topic

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Issue 4 • Date Nov 1996

Filter Results

Displaying Results 1 - 13 of 13
  • Performance improvement of the memory hierarchy of RISC-systems by application of 3-D technology

    Page(s): 709 - 718
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1248 KB)  

    In this paper, the performance of the memory hierarchy of RISC-systems for implementations employing three-dimensional (3-D) technology is investigated. Relating to RISC-systems, 3-D technology enables the integration of multiple chip-layers of memory together with the processor in one 3-D IC. In a first step, the second-level cache can be realized in one 3-D IC with processor and first-level cache. This results in a considerable reduction of the hit time of the second-level cache due to a decreased access time and a larger allowable bus-width to the second-level cache. In a further step, the main memory can be integrated which relieves restrictions with respect to the bus-width to main memory. The use of 3-D technology for system implementation is observed to have a significant impact on the optimum design and performance of the memory hierarchy, Based on an analytical model, performance improvements on the order of 20% to 25% in terms of the average time per instruction are evaluated for implementations employing 3-D technology over conventional ones. It is concluded that 3-D technology is very attractive for future RISC-system generations View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Solder joint reliability of flip chip and plastic ball grid array assemblies under thermal, mechanical, and vibrational conditions

    Page(s): 728 - 735
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1356 KB)  

    The thermal, mechanical, and vibrational responses of flip chip and plastic ball grid array (PBGA) solder joints have been determined in this study. The effects of overload environmental stress factors on the mechanical responses of the solder joints have been determined by bending and twisting experiments. The effects of shipping environmental stress factors on the vibrational responses of the solder joints have been determined by out-of-plane vibration experiments. Also, the thermal fatigue behavior of solder joints have been investigated by nonlinear finite element (FE), Coffin-Manson, and fracture mechanics methods View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new anisotropic conductive film with arrayed conductive particles

    Page(s): 752 - 757
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (960 KB)  

    A new anisotropic conductive film (ACF) incorporating arrayed metal conductors in an adhesive polymer film is proposed. A photoresist pattern with a number of round holes arrayed in triangular arrangement is formed on a stainless steel substrate. The holes are then electroplated to form metal bumps, using the substrate as a cathode. After removal of the photoresist, the substrate is laminated with a solid adhesive film. Finally, the ACF of arrayed metal bumps is obtained when the adhesive film is peeled off and the metal bumps are transferred from the substrate to the adhesive film. The superior interconnection properties of the proposed ACF, compared with conventional ACFs that rely on randomly distributed conductive particles, are attributed to the arrayed, uniformly sized particles in the adhesive film View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • VLSI interconnect design automation using quantitative and symbolic techniques

    Page(s): 803 - 812
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1076 KB)  

    This paper presents a framework for design automation of VLSI interconnect geometries. Crosstalk, overshoot, undershoot, signal delay, and line impedance are design performance parameters under consideration. Since the dependence of electrical performance parameters on geometry is not easily defined, both qualitative and quantitative techniques are used. Two knowledge bases are introduced-a model and simulation base. The model base contains models used for terminations, transmission line parameter extractors, and transmission lines. The simulation knowledge base contains a set of approximations and routines for the exact evaluation of electrical performance parameters. Procedures are introduced for the automatic extraction of applicable models and simulation techniques in the design process. An unconstrained optimization routine is used as a design search technique. The approach presented here gives faster results than approaches shown in literature, with little sacrifice of accuracy View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Laser weldability analysis of high-speed optical transmission device packaging

    Page(s): 758 - 763
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB)  

    A 2.5 Gb/s distributed feedback laser diode (DFB-LD) module was used as a test package to develop laser welding techniques. Various package weld joint geometries, such as lap, fillet, butt, and fillet-lap, were designed and welded to investigate the optimal package configuration that leads to the maximum coupling efficiency and minimum weld shift. Furthermore, the welded joints at a given set of laser parameters were cross-sectioned for metallurgical analysis, such as weld penetration and microcracks, for verification of the weld joint integrity. Through such analysis, some important laser welding parameters, such as depth-of-penetration (DOP), heat-affected zone (HAZ), shear-strength, and solidification formation of the weld pool were analyzed. Also, as the result of investigating 56 laser welded DFB-LD submodules, optimal laser parameters, and the suitable joint geometry for this package could be determined with the average weld shift less than 0.19 dB, which translates to less than 1.0 μm in radial displacement. These laser welded packages exhibited an excellent tracking stability during environmental testing, which consequently resulted in obtaining a desirable bit-error rate (BER) during the data transmission performance analysis View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Packaging alternatives to large silicon chips: tiled silicon on MCM and PWB substrates

    Page(s): 699 - 708
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (900 KB)  

    Recent advances in area array chip bonding combined with the availability of high density substrates facilitate novel approaches to partitioning future systems. We examine one such new paradigm here: tiled silicon, in which system integration is achieved by tiling a set of chips together using area bonding on high density substrates rather than by pursuing single chip integration. We simulate the partitioning of large silicon/complementary metal-oxide-semiconductor (Si/CMOS) chips into tiled arrays of silicon chips, including in the analysis wiring lengths, electrical interconnect issues, I/O requirements, including drivers and electrostatic discharge (ESD) protection, wiring capacity, floorplans, wiring demand, escape, manufacturing yield, cost, and other electrical and thermal issues. Partitions are assumed to be interconnected via random logic, bus or memory type net topologies. Our results clearly show that it is possible to effectively tile silicon chips, when they are connected by reduced Rent exponent random logic, buses, or memory type net topologies. Systems with high interconnect demand, and thus little or no functional integration, cannot be tiled because of problems with larger chip real estate for drivers for off-chip lines and off-chip wiring capacity View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computing inductive noise of CMOS drivers

    Page(s): 789 - 802
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB)  

    The inductive noise (i.e., ΔI noise, simultaneous switching noise, or ground bounce) developed between the ground plane in the chip and the ground plane in the printed wiring board (PWB) seriously limits the number of on-chip drivers or bits that can be switched simultaneously in the same direction. This is especially the case for the ubiquitous complementary metal-oxide-semiconductor (CMOS) technology, which now forms the basis of VLSI. This paper presents a new electrical model for computing inductive noise associated with CMOS technology. The model is especially useful for computing inductive noise during chip-to-chip communication when n CMOS drivers are switched in the same direction at an arbitrary, monotonic set of times {t1=0, t2, t3, ···, tn} to form controlled skewing sequences View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Defect formation mechanisms in laser welding techniques for semiconductor laser packaging

    Page(s): 764 - 769
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB)  

    In this work, the authors experimentally investigate defect formation mechanisms in spot-welding techniques for semiconductor laser packaging. Results obtained from the stainless-to-stainless steel joints indicate that the dimension of hole formation depends on the laser power density, and the hole disappears as the power density is below 3×105 W/cm2. In the stainless-to-KovarTM joints, surface cracks are eliminated by reducing the gold thickness from the KovarTM before welding, while the centerline cracks in the fusion zone are eliminated by the air gap tightness between the KovarTM and stainless steel. The excess laser energy is the possible cause for hole formation. The low solubility of gold in the KovarTM and the large air gap between the joints are the possible causes for surface cracks and enhancing centerline crack propagation, respectively. A technique for reduction of post weld shift (PWS) in semiconductor laser packaging is also presented. Preliminary reliability data demonstrated that these laser packages, which do not have hole and crack defects in the welded joints, are reliable View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-cost flip-chip on board

    Page(s): 736 - 746
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1444 KB)  

    For hand-held communication products, like the DECT telephone system, flip-chip on board offers minimization of both the package size and the occupied area on the boards. As a result of the reduction in interconnection lengths, the self-inductance is reduced. For high volume production, the compatibility of the flip-chip mounting technique with standard surface mount technology (SMT) reflow is essential. During reflow, the eutectic PbSn bump wets along the copper track, so the stand-off between integrated circuits (IC's) and the board is accurately defined by the layout of the board and the dimensions of the bump. The eutectic PbSn flip-chip processing is evaluated by impedance and cross-talk measurements, and in several reliability tests. For the electrical measurements, a zero-IF front-end IC is used. Wide-band measurements of the input impedance showed that the residual parasitics associated with the eutectic PbSn bumps are negligible compared with the parameters of the internal IC components. To accommodate the residual stresses from differences in coefficient of thermal expansion (CTE), the gap between the IC and the substrate is underfilled. This underfill material marginally affects the electrical behavior of the IC at frequencies up to a few GHz. As expected, a slight increase in the residual capacitance is observed. The effect of the underfill is studied by both temperature cycle and shock tests; cumulative failure distributions have been plotted. Results show that the adhesion properties and flow characteristics of the underfill material are the dominating factors for the number of cycles to failure. By selecting the proper underfill and curing conditions, the eutectic PbSn flip-chip construction can meet the test requirements for consumer communication products View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Application of path integrals in modeling transmission line loss

    Page(s): 775 - 788
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (856 KB)  

    In signal integrity applications involving the modeling and analysis of high-speed digital interconnects, it is necessary to include the effects of nonideal transmission line behavior due to, for example, the effects of ohmic, dielectric, and skin effect losses. This paper describes a new approach to this problem by employing a path integral formulation to both model lossy and nonuniform transmission line behavior. The algorithm resulting from the application of this formulation is accurate, stable, computationally efficient, and applicable to time domain modeling of interconnect in digital systems View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance modeling of the interconnect structure of a three-dimensional integrated RISC processor/cache system

    Page(s): 719 - 727
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (976 KB)  

    In order to investigate the performance potential of three-dimensional integrated circuits (3-D IC's) for high performance computer systems a comparative study of the interconnect structure of a RISC processor/cache system is presented. The wiring structure, wiring dimensions and line drivers are optimized for 3-D system alternatives. The realizations are compared to a conventional printed circuit board (PCB) and a typical multichip module (MCM) implementation of the system with respect to cache access time and power dissipation. The impact of electrical parameters of interconnection lines as well as associated package parasitics on second level cache read access is investigated. Case studies show reductions of effective switching capacitances of more than an order of magnitude and reductions of second level cache access time of over 30% for optimized 3-D systems compared to conventional PCB realizations View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Approaching a uniform bump height of the electroplated solder bumps on a silicon wafer

    Page(s): 747 - 751
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (756 KB)  

    The investigation of the manipulation of the physical structure of an electrolytic cell to achieve uniform solder bumps on a silicon wafer is discussed. The variables investigated include: the applied current density, the distance and the area ratio of the electrode, and the width ratio between the cathode and the bath. The width ratio of one between the cathode and the bath was found to lead to a uniform bump height throughout the wafer. The reflow of the as-plated solder bumps raised bump height and produced uniform ball-shaped bumps. The deviations of the bump height on a wafer are within 5% after reflow of the uniform as-plated bumps View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Extraction of the capacitance matrix of multiconductor interconnection lines for high-speed IC system design

    Page(s): 770 - 774
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    A simplified and very effective method for the extraction of the capacitance matrix of multiconductor interconnection lines for high-speed integrated circuit (IC) system design is described in this paper. Because of the combination of the approximate spatial domain Green's function of multilayered dielectric media and the three physically meaningful charge basis functions per conductor edge, preprocessing can take place. Thus, the capacitance matrix can then be quickly computed with high accuracy. Examples show that this method is very efficient and accurate for circuit parameter extraction of high-speed IC interconnect structures View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope