Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on
Issue 4 • Date Nov 1996
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Displaying Results 1 - 13 of 13
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Extraction of the capacitance matrix of multiconductor interconnection lines for high-speed IC system design
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PDF (448 KB)
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Performance modeling of the interconnect structure of a three-dimensional integrated RISC processor/cache system
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PDF (976 KB)
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Packaging alternatives to large silicon chips: tiled silicon on MCM and PWB substrates
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PDF (900 KB)
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Performance improvement of the memory hierarchy of RISC-systems by application of 3-D technology
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PDF (1248 KB)
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Computing inductive noise of CMOS drivers
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PDF (968 KB)
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Defect formation mechanisms in laser welding techniques for semiconductor laser packaging
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PDF (940 KB)
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Approaching a uniform bump height of the electroplated solder bumps on a silicon wafer
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PDF (756 KB)
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Solder joint reliability of flip chip and plastic ball grid array assemblies under thermal, mechanical, and vibrational conditions
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PDF (1356 KB)
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Low-cost flip-chip on board
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PDF (1444 KB)
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Aims & Scope
IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging was published 1994-1998. The latest title for this publication is IEEE Transactions on Advanced Packaging.
