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Selected Topics in Quantum Electronics, IEEE Journal of

Issue 1 • Date April 1996

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Displaying Results 1 - 15 of 15
  • An ATM-based intelligent optical backplane using CMOS-SEED smart pixel arrays and free-space optical interconnect modules

    Publication Year: 1996 , Page(s): 85 - 96
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1620 KB)  

    The architecture, smart pixel array chip design, and optical design of an intelligent free-space digital optical backplane for ATM switching are presented. The smart pixel chip uses reflective SEED (self-electrooptic effect device) optical modulators and detectors flip-chip bonded to CMOS circuitry. This chip is one of the most complex designs ever reported in this technology, and it operates at a simulated backplane clock rate of 125 MHz. The low-loss optical system employs f/4 diffractive minilenses and microlenses to interconnect clusters of smart pixels, and it is shown to allow 2060 connections per chip if 1-cm2-sized smart pixel chips are used. This gives a predicted bisection bandwidth of around 1 Tb/s across a 10-in circuit board edge for a full-sized system. View full abstract»

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  • Correction to "Inhomogeneous Exciton Broadening and Mean Free Path in In/sub 1-x/Ga/sub x/As/sub y/"

    Publication Year: 1996
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (105 KB)  

    First Page of the Article
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  • Telecommunications applications of ferroelectric liquid-crystal smart pixels

    Publication Year: 1996 , Page(s): 35 - 46
    Cited by:  Papers (9)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1520 KB)  

    Ferroelectric liquid crystal over silicon smart pixels offers potential advantages over conventional electronic and waveguide approaches to telecommunications switching. The role of such smart-pixel architectures in space/wavelength optical interconnect and in high-performance ATM switches based on interconnection of optically accessed memory is discussed View full abstract»

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  • Challenges in optically interconnecting electronics

    Publication Year: 1996 , Page(s): 3 - 13
    Cited by:  Papers (34)  |  Patents (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1180 KB)  

    The challenges associated with the development of free-space optically interconnected electronics are discussed. These include finding an application for which optics offers an improved performance, developing optical transceivers, and developing suitable optics and mechanics. The main focus of the paper is the discussion of some novel approaches that smart pixels offer to increase alignment tolerance View full abstract»

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  • A hybrid-SEED smart pixel array for a four-stage intelligent optical backplane demonstrator

    Publication Year: 1996 , Page(s): 97 - 105
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB)  

    This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given View full abstract»

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  • Optical receivers for optoelectronic VLSI

    Publication Year: 1996 , Page(s): 106 - 116
    Cited by:  Papers (35)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    We describe our work on the design and testing of optical receivers for use in optoelectronic VLSI. The local nature of the optoelectronic VLSI system permits novel receiver designs, incorporating multiple optical beams and/or synchronous operation, while the requirement of realizing large numbers of receivers on a single chip severely constrains area and power consumption. We describe four different receiver designs, and their different operating modes. Results include 1-Gb/s high-impedance, two-beam diode-clamped FET-SEED receivers, single and dual-beam transimpedance receivers realized with a hybrid attachment of multiple-quantum well devices to 0.8-μm linewidth CMOS operating to 1 Gb/s, and synchronous sense-amplifier-based optical receivers with low (~1 mW) power consumption. Finally, we introduce a measure of receiver performance that includes area and power consumption View full abstract»

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  • Two-dimensional finite-element modeling of nematic liquid crystal devices for optical communications and displays

    Publication Year: 1996 , Page(s): 128 - 134
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (668 KB)  

    A two-dimensional finite-element code is presented for the steady-state analysis of liquid crystal structures in nonuniform electric fields. It is based on a free-energy formulation which includes all three elastic constants and can deal with pure nematic, twisted nematic, and cholesteric liquid crystal materials. The enhanced capabilities of our code allow the design of composite structures made of both dielectric and liquid crystal materials and with arbitrary configuration of electrodes. Unwanted effects, such as the formation of disclination lines in the director orientation, can be accurately predicted. The method has been applied for analyzing pure nematic liquid crystal microlenses with variable focal length and twisted nematic liquid crystal cells for display applications. Numerical results show that a careful choice of the device structures can avoid the formation of defects and improve their performance View full abstract»

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  • Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap

    Publication Year: 1996 , Page(s): 55 - 76
    Cited by:  Papers (98)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2200 KB)  

    Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs-AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic transceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of future CMOS technology View full abstract»

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  • Processing architectures for smart pixel systems

    Publication Year: 1996 , Page(s): 24 - 34
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2800 KB)  

    Smart pixel architectures offer important new opportunities for low-cost, portable image processing systems. They provide greater I/O bandwidth and computing performance than systems based on CCD and microprocessors. However, finding a balance between performance, flexibility, efficiency, and cost depends on an evaluation of target applications. This paper describes several promising architectural approaches for the realization of videoputer systems and outlines example implementations being pursued at the Georgia Institute of Technology View full abstract»

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  • Progress in the smart pixel technologies

    Publication Year: 1996 , Page(s): 14 - 23
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2332 KB)  

    The purpose of this paper is to review the recent progress in the developing smart pixel technologies. The paper begins by reviewing some of the rapidly evolving smart pixel terminologies. It then describes several of the smart pixel technologies that have recently emerged. Finally, it outlines the performance of these technologies in both device complexity and aggregate capacity. The reviewed SPA technologies include both the modulator-based FET-SEED, hybrid CMOS-SEED, and LCOS smart pixels and the source-based hybrid VCSEL/MSM, ELO, flip-chip-bonded VCSEL/MSM, and monolithic MSM/MESFET/VCSEL smart pixels View full abstract»

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  • High-speed optoelectronic VLSI switching chip with >4000 optical I/O based on flip-chip bonding of MQW modulators and detectors to silicon CMOS

    Publication Year: 1996 , Page(s): 77 - 84
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (908 KB)  

    We present the first high-speed optoelectronic very large scale integrated circuit (VLSI) switching chip using III-V optical modulators and detectors flip-chip bonded to silicon CMOS. The circuit, which consists of an array of 16×1 switching nodes, has 4096 optical detectors and 256 optical modulators and over 140K transistors. All but two of the 4352 multiple-quantum-well diodes generate photocurrent in response to light. Switching nodes have been tested at data rates above 400 Mb/s per channel, the delay variation across the chip is less than ±400 ps, and crosstalk from neighboring nodes is more than 45 dB below the desired signal. This circuit demonstrates the ability of this hybrid device technology to provide large numbers of high-speed optical I/O with complex electrical circuitry View full abstract»

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  • A monolithically integrated smart pixel using an MSM-PD, MESFET's, and a VCSEL

    Publication Year: 1996 , Page(s): 121 - 127
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB)  

    We have developed a smart pixel that monolithically integrates a metal-semiconductor-metal (MSM) photodetector, metal-semiconductor field effect transistors (MESFET's), and a vertical-cavity surface-emitting laser (VCSEL). This device can perform both NOR- and OR-types of operation with a thresholding function. Optimal device parameters are obtained by using a SPICE simulation. Calculations show that the switching time is mainly limited by the CR time constant of the input stage, which consists of the MSM photodetector, the load-resistor, and the MESFET connected to the MSM photodetector. The fabricated device attained a contrast ratio of more than 30 dB with optical gain. The 3-dB bandwidth was 220 MHz and the switching energy was 700 fJ at an operation frequency of 100 MHz. We also discuss the power consumption and the packing density of the smart pixel including the VCSEL as a function of operation frequency. A MESFET that has high fT with low bias voltage and a VCSEL that has a low threshold current while maintaining the wall-plug efficiency are necessary to obtain a higher performance device View full abstract»

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  • Smart pixel optoelectronic receiver based on a charge sensitive amplifier design

    Publication Year: 1996 , Page(s): 117 - 120
    Cited by:  Papers (4)  |  Patents (89)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    The application of charge sensitive amplifier techniques to the design of receivers within smart pixel optoelectronic systems is presented. An example optical input amplifier is given which should provide high sensitivity (±0.3 μA differential), low power consumption (0.6 mW) and small area usage (50 μm×20 μm) for operation at a conventional CMOS bit rate of 100 Mb/s. The minimum (simulated) optical switching energy is 6 fJ View full abstract»

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  • High-density digital free-space photonic-switching fabrics using exciton absorption reflection-switch (EARS) arrays and microbeam optical interconnections

    Publication Year: 1996 , Page(s): 47 - 54
    Cited by:  Papers (2)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1048 KB)  

    We describe a compact digital free-space photonic-switching module that uses microbeam optical interconnections based on stacked planar optics and exciton absorption reflection-switch (EARS) arrays. Microbeam optical interconnections become increasingly attractive as the number of optical input and output (I/O) ports increases because of their small size. The EARS device provides the digital-signal regeneration needed for constructing a multistage switching network. This paper mainly describes the experimental investigation of a prototype switch having a two-stage, 16-input, 16-output structure (four sets of 4×4 switches), with highly dense two-dimensional fiber array pigtails acting as high-density optical I/Os. The prototype is approximately 30×90×22 mm [60 cc]. A relay lens array inserted between stages eliminates the beam spreading caused by diffraction, which decreases the required positioning accuracy for the optomechanical packaging. Two-stage switching at a data transmission rate of 4 Mb/s has been demonstrated. Increasing the operating speed of the switch and introducing an easy assembly method to reduce assembly costs are future enhancements View full abstract»

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  • Polarization sensing with resonant cavity enhanced photodetectors

    Publication Year: 1996 , Page(s): 135 - 140
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    We describe a new method of sensing the linear polarization of light using resonant cavity enhanced (RCE) photodetectors. The RCE detectors are constructed by integrating a thin absorption region into an asymmetric Fabry-Perot cavity. The top reflector is formed by the semiconductor air interface while the bottom mirror is a distributed Bragg reflector (DBR). Quantum efficiency of these RCE devices can be controlled by tuning the cavity length by recessing the top surface of the detector for off-normal incidence of light the reflectivity of the semiconductor-air interface can be significantly different for TE(s) and TM(p) polarizations. A pair of monolithically integrated RCE photodetectors with cavity lengths tuned for resonance and antiresonance provide a large contrast in response to TE and TM polarizations. An alternative polarization sensor can be formed by vertically integrating a conventional and a RCE photodetector. We show that a large contrast in the TE/TM responsivities of the vertical cavity polarization detectors (VCPD) can be achieved, thus combining detection and polarization sensing in a single mesa semiconductor device. These devices alleviate the problems associated with the bulkiness and critical alignment constraints of the conventional sensors based on polarizing filters or splitters and have potential for fabrication of monolithic smart pixels and imaging arrays View full abstract»

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Aims & Scope

Papers published in the IEEE Journal of Selected Topics in Quantum Electronics fall within the broad field of science and technology of quantum electronics of a device, subsystem, or system-oriented nature.

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Meet Our Editors

Editor-in-Chief
Luke F. Lester
Virginia Polytechnic Institute & State University