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Computers, IEEE Transactions on

Issue 10 • Date Oct 1996

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Displaying Results 1 - 12 of 12
  • Harvest rate of reconfigurable pipelines

    Publication Year: 1996 , Page(s): 1200 - 1203
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (376 KB)  

    For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. The authors give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: there are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probabi... View full abstract»

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  • Load sharing in hypercube-connected multicomputers in the presence of node failures

    Publication Year: 1996 , Page(s): 1203 - 1211
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (804 KB)  

    The paper addresses two important issues associated with load sharing (LS) in hypercube-connected multicomputers: (1) ordering fault-free nodes as preferred receivers of “overflow” tasks for each overloaded node and (2) developing an LS mechanism to handle node failures. Nodes are arranged into preferred lists of receivers of overflow tasks in such a way that each node will be selected... View full abstract»

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  • An architecture for tolerating processor failures in shared-memory multiprocessors

    Publication Year: 1996 , Page(s): 1101 - 1115
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1860 KB)  

    This paper focuses on the problem of fault tolerance in shared memory multiprocessors, and describes an architecture designed for transparently tolerating processor failures. The Recoverable Shared Memory (RSM) is the novel component of this architecture, providing a hardware supported backward error recovery mechanism which minimizes the propagation of recovery when a processor fails. The RSM per... View full abstract»

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  • On linear dependencies in subspaces of LFSR-generated sequences

    Publication Year: 1996 , Page(s): 1212 - 1216
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (428 KB)  

    The probability of linear dependency in subsequences generated by linear feedback shift registers is examined. It is shown that this probability for a short subsequence, e.g., a sequence defined by the length of a scan chain, can be much higher than that for an entire m-sequence View full abstract»

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  • Simulation and generation of IDDQ tests for bridging faults in combinational circuits

    Publication Year: 1996 , Page(s): 1131 - 1140
    Cited by:  Papers (25)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (900 KB)  

    In the absence of information about the layout, test generation and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for simulating IDDQ tests for all two-line bridging faults in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting ... View full abstract»

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  • Adaptive system-level diagnosis for hypercube multiprocessors

    Publication Year: 1996 , Page(s): 1157 - 1170
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1340 KB)  

    System-level diagnosis is an important technique for fault detection and location in multiprocessor computing systems. Efficient diagnosis is highly desirable for sustaining the original system power. Moreover, effective diagnosis is particularly important for a multiprocessor system with high scalability but low connectivity. Most of the existing results are not applicable in practice because of ... View full abstract»

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  • Theory of transparent BIST for RAMs

    Publication Year: 1996 , Page(s): 1141 - 1156
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1580 KB)  

    I present the theoretical aspects of a technique called transparent BIST for RAMs. This technique applies to any RAM test algorithm and transforms it into a transparent one. The interest of the transparent test algorithms is that testing preserves the contents of the RAM. The transparent test algorithm is then used to implement a transparent BIST. This kind of BIST is very suitable for periodic te... View full abstract»

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  • Architecture technique trade-offs using mean memory delay time

    Publication Year: 1996 , Page(s): 1089 - 1100
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1160 KB)  

    Many architecture features are available for improving the performance of a cache-based system. These hardware techniques include cache memories, processor stalling characteristics, memory cycle time, the external databus width of a processor, and pipelined memory system, etc. Each of these techniques affects the cost, design, and performance of a system. We present a powerful approach to assess t... View full abstract»

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  • A performance evaluation of RAID architectures

    Publication Year: 1996 , Page(s): 1116 - 1130
    Cited by:  Papers (36)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1360 KB)  

    In today's computer systems, the disk I/O subsystem is often identified as the major bottleneck to system performance. One proposed solution is the so called redundant array of inexpensive disks (RAID). We examine the performance of two of the most promising RAID architectures, the mirrored array and the rotated parity array. First, we propose several scheduling policies for the mirrored array and... View full abstract»

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  • Scheduling master-slave multiprocessor systems

    Publication Year: 1996 , Page(s): 1195 - 1199
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (456 KB)  

    The author defines the master-slave multiprocessor scheduling model in which a master processor coordinates the activities of several slave processors. O(n log n) centralized, deterministic, batch-oriented algorithms are developed for some of the problems formulated. Some others are shown to be NP-hard View full abstract»

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  • An analytical model for designing memory hierarchies

    Publication Year: 1996 , Page(s): 1180 - 1194
    Cited by:  Papers (28)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1316 KB)  

    Memory hierarchies have long been studied by many means: system building, trace driven simulation, and mathematical analysis. Yet little help is available for the system designer wishing to quickly size the different levels in a memory hierarchy to a first order approximation. We present a simple analysis for providing this practical help and some unexpected results and intuition that come out of ... View full abstract»

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  • A bidirectional associative memory based on optimal linear associative memory

    Publication Year: 1996 , Page(s): 1171 - 1179
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (752 KB)  

    A bidirectional associative memory is presented. Unlike many existing BAM algorithms, the presented BAM uses an optimal associative memory matrix in place of the standard Hebbian or quasi correlation matrix. The optimal associative memory matrix is determined by using only simple correlation learning, requiring no pseudoinverse calculation. Guaranteed recall of all training pairs is ensured by the... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org