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Computers and Digital Techniques, IEE Proceedings -

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Computers and Digital Techniques, IEE Proceedings -

Issue 5 • Date Sep 1996

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Title History

Superscalar instruction issue in an asynchronous microprocessor

Testable on-the-fly carry-save multiplier by alternating input data

Functionally asynchronous array processor for morphological filtering of greyscale images

Asynchronous FPGA architectures

Asynchronous implementation of the SCPP-A counterflow pipeline processor

Verification of speed-independent data-path circuits

Design of a low-latency asynchronous adder using speculative completion

Architectural considerations for a self-timed decoupled processor

Rotary pipeline processors

Delayed precise invalidation-a software cache coherence scheme

Estimating power consumption of CMOS circuits modelled as symbolic neural networks

Dynamic scheduling in RISC architectures

Design and implementation of a GaAs systolic floating-point processing element

Functional testing of pipelined processors

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