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Selected Areas in Communications, IEEE Journal on

Issue 3 • Date Apr 1988

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Displaying Results 1 - 17 of 17
  • Gigabit receiver ICs for optical communications

    Publication Year: 1988 , Page(s): 460 - 476
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    The authors discuss gigabit receiver ICs for optical communications, focusing on their circuit and package design, the performance of receivers that were fabricated, and their application to a 1.6 Gb/s optical receiver. The key technologies for the receivers are discussed, and a design based on these key technologies is proposed. The proposed design is used to fabricate six receiver ICs (eight chips) using an ultra-high-speed bipolar process with transistors having a unity gain bandwidth of 6-8 GHz. The receivers are suitable for long-haul optical transmission at bit rates up to 1.6 Gb/s. Experimental results show that the 1.6 Gb/s receiver has an optical dynamic range of more than 23 dB without any adjustment, and the received average optical power required to maintain a 10-11 error rate is less the -31 dBm View full abstract»

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  • High-speed signal processing using systolic arrays over finite rings

    Publication Year: 1988 , Page(s): 504 - 512
    Cited by:  Papers (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    A modular architecture for very fast digital signal processing (DSP) elements are presented. The computation is performed over finite rings (or fields) and is able to emulate processing over the integer ring using residue number systems. The computations are restricted to closed operations (ring or field binary operators) with the ability to perform limited scaling operations. Computations naturally defined over finite mathematical systems are also easily implemented using this approach. The technique evolves from the decomposition of each closed calculation using the ring/field associativity property. Linear systolic arrays, formed with multiple elements, each of a single generic form, are used for all calculations. The pipeline cycle is determined from the generic cell and is predicted to be very fast by a critical path analysis. The cells are matched to the VLSI medium, and the resulting array structures are very dense. Examples of DSP applications are given to illustrate the technique, and example cell and array VLSI layouts are presented for a 3-μm CMOS process View full abstract»

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  • A flexible adaptive FIR filter VLSI IC

    Publication Year: 1988 , Page(s): 494 - 503
    Cited by:  Papers (6)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (896 KB)  

    The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with finite impulse response (FIR) and adaptive FIR digital filtering applications. The DSP56200 is implemented in high-performance, low-power 1.5-μm HCMOS technology and is available in a 28-pin DIP package. The on-chip computation unit includes a 97.5-ns 24-bit×24-bit coefficient RAM, and a 256-bit×16-bit data RAM. Three modes of operation allow the part to be used as a single, dual, or single adaptive FIR filter, with up to 256 taps per chip. In the adaptive mode, the part performs the FIR filtering and least-mean-square (LMS) coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19-kHz sampling rate, 256-tap adaptive FIR filter. A programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceler configuration is presented. Typical applications of the part are also described View full abstract»

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  • A single-board video signal processor module employing newly developed LSI devices

    Publication Year: 1988 , Page(s): 513 - 519
    Cited by:  Papers (13)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    A single-board 14.3-MOPS (million operations per second) video signal processor module (VSPM) has been developed. The module is fully microprogrammable and processes up to a 128 pel×128 pel subimage every 16.7 ms. Using a number of homogeneous VSPMs aligned in parallel, a real-time video signal processing environment is provided on the basis of an overlap-save or overlap-add technique. An experimental system has been constructed in order to demonstrate the signal processor approach's effectiveness for video signals by implementing picture coding algorithms. Due to software control capability, various kinds of picture coding techniques can be evaluated by the system View full abstract»

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  • VLSI implementation of a maximum-likelihood decoder for the Golay (24, 12) code

    Publication Year: 1988 , Page(s): 558 - 565
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    J.H. Conway and N.J.A. Sloane (1986) have introduced an algorithm for the exact maximum-likelihood decoding of the Golay (24, 12) code in the additive white Gaussian noise channel that requires significantly fewer computations than previous algorithms. An efficient bit-serial VLSI implementation of this algorithm is described. The design consists of two chips developed using path-programmable logic (PPL) and an associated system of automated design tools for three-μm NMOS technology. It is estimated that this decoder will produce an information bit every 1.6-2.4 μs. Higher speeds can be achieved by using a faster technology or by replicating the chips to perform more operations in parallel View full abstract»

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  • A bit-slice architecture for sigma-delta analog-to-digital converters

    Publication Year: 1988 , Page(s): 520 - 526
    Cited by:  Papers (14)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    The sigma-delta analog-to-digital converters is based on filtering and undersampling by the digital section of the one-bit output stream coming from the modulation. The structure of this section, consisting of a sine cubic FIR filter decimator followed by an IIR decimator section, is discussed. It is shown that from both signal processing and hardware implementation viewpoints it is advantageous to have the decimation factor of the first stage as large as possible. A bit-slice implementation of the decimation stages is given. It can be easily expanded when higher bit resolutions are required View full abstract»

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  • A 16×16 crosspoint switch for ternary encoded signals

    Publication Year: 1988 , Page(s): 566 - 571
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    A crosspoint-switching chip that can switch bipolar, alternate mark inversion encoded (AMI) signals directly, is described. AMI encoding is a form of ternary, return-to-zero (RZ) coding where a binary zero is represented by an absence of a pulse and ones are represented with an alternating sequence of positive and negative pulses. Bipolar signals are used widely in interoffice telecommunications such as the T1, T1C, T2, and T3 digital transmission systems. The switching chip has 16 input and 16 output channels. Control of the chip allows any input to be connected to any output or outputs, providing a nonblocking connection. The architecture allows for expansion of the crosspoint array by paralleling several chips. The chip, fabricated using a standard 3-μm CMOS technology, is capable of handling data rates up to 15 Mb/s per channel, has about 17000 transistors, and has an area of about 32.5 mm2 View full abstract»

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  • Architectures for exponentiation in GF(2m)

    Publication Year: 1988 , Page(s): 578 - 585
    Cited by:  Papers (23)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    Several VLSI architectures for performing exponentiation in GF(2 m) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2ei power, O⩽im-1, are precomputed and stored so that the intermediate product terms can be calculated in a parallel fashion. For the two approaches, both synchronous and asynchronous implementations are presented using standard and normal bases. The discussion emphasizes the design and performance tradeoffs incurred in developing such architectures View full abstract»

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  • A fast algorithm for the Fourier transform over finite fields and its VLSI implementation

    Publication Year: 1988 , Page(s): 572 - 577
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    The Fourier transform over finite fields is mainly required in the encoding and decoding of Reed-Solomon and BCH codes. An algorithm for computing the Fourier transform over any finite field GF(pm) is introduced. It requires only O(n(log n)2/4) additions and the same number of multiplications for an n-point transform and allows in some fields a further reduction of the number of multiplications to O(n log n). Because of its highly regular structure, this algorithm can be easily implementation by VLSI technology View full abstract»

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  • Circuit design and transmission performance of ISDN basic interface

    Publication Year: 1988 , Page(s): 468 - 475
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB)  

    An LSI-based user-network interface circuit, applicable to a network terminal (NT) for the integrated services digital network (ISDN) basic interface is developed. Adaptive timing extraction, with a simplified polyphase phase-locked oscillator, is introduced into the circuit for application to both point-to-point and passive bus configurations. This circuit does not require any manual adjustment. In addition to the primitives defined by CCITT between layers one and two, a new primitive is adopted for controlling the transmission of information. This primitive avoids premature transmission due to processing delays in the exchange terminal (ET). The above functions are fabricated on a CMOS gate-array LSI chip with 4000 gates. The performance of the interface circuit is confirmed with special attention to transmission and electrical characteristics View full abstract»

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  • Locally connected VLSI architectures for the Viterbi algorithm

    Publication Year: 1988 , Page(s): 527 - 537
    Cited by:  Papers (56)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1084 KB)  

    The Viterbi algorithm is a well-established technique for channel and source decoding in high-performance digital communication systems. Implementations of the Viterbi algorithm on three types of locally connected processor arrays are described. The restriction is motivated by the fact that both the cost and performance metrics of VLSI favour architectures in which on-chip interprocessor communication is localized. Each of the structures presented can accommodate arbitrary alphabet sizes and algorithm memory lengths View full abstract»

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  • A coded data transceiver for the Star Local Area Network (StarLAN)

    Publication Year: 1988 , Page(s): 610 - 619
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (756 KB)  

    The system requirements of the physical layer of a star-connected local area network (StarLAN) are examined. The network forms a 1-Mb/s component of the IEEE 802.3 CSMA/CD (carrier-sense multiple-access with collision detection) system. The new standard allows CSMA/CD network protocols to be used over telephone twisted pairs for office or industrial digital communications. The use of this protocol means that existing local area network controllers and their higher level operations will be immediately compatible with StarLAN operation. The philosophy and functionality of the AM7961 StarLAN coded data transceiver is discussed in the context of the StarLAN environment and multipoint extension (MPE), a bus-oriented extension. MPE is a demanding requirement which needs special consideration in the collision detection system used by the chip. It is graphically shown why these requirements cannot easily be met by conventional techniques. The results on the test demonstrate that the overvoltage sensing system used in the chip overcomes the difficulties encountered View full abstract»

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  • New architectures for fast convolutional encoders and threshold decoders

    Publication Year: 1988 , Page(s): 457
    Cited by:  Papers (5)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB)  

    Several new architectures for high-speed convolution encoders and threshold decoders are developed. In particular, it is shown that new architectures featuring both parallelism and pipelining are promising from a speed point of view. These architectures are practical for a wide range of coding rates and constant lengths. Two integrated circuits featuring these architectures have been designed and fabricated in a CMOS 3-μm technology. The two circuits have been tested and can be used to build convolutional encoders and definite threshold decoders operating at data rates above 100 Mb/s. It is shown that with these architectures, encoders and threshold decoders could easily be designed to operate at data rates above 1 Gb/s View full abstract»

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  • Communication network issues and high-density interconnects in large-scale distributed computing systems

    Publication Year: 1988 , Page(s): 587 - 609
    Cited by:  Papers (8)  |  Patents (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2068 KB)  

    The authors discuss the impact of the physical interconnection environment through which the concurrent processes among locally distinct computing nodes of large-scale multicomputer systems are coupled. The communication capabilities implied for massively parallel computing systems by fine-grain task partitioning and by fine-grained communications are discussed in detail. Wafer-scale and hybrid wafer-scale system technologies which would support such communications are described View full abstract»

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  • A nonsorting VLSI structure for implementing the (M, L ) algorithm

    Publication Year: 1988 , Page(s): 538 - 546
    Cited by:  Papers (18)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    A nonsorting structure for implementing the (M, L) algorithm is presented. The processing is based on a survivor selection operation that incorporates parallelism and has an execution time proportional to the product of the logarithm of bM (the number of contender paths), and k (the number of bits used for path metrics). Aside from the path extender(s), the processor area is only a small fraction of the total chip area; most is simply for required storage of path histories and metrics. This means that the structure can support a large M on a single chip. In addition, the structure can be extended to larger M by stacking rows of a few different types of custom chips View full abstract»

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  • Efficient bit-level systolic array implementation of FIR and IIR digital filters

    Publication Year: 1988 , Page(s): 484 - 483
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    Bit-level systolic architectures based on an inner-product computation scheme for finite-impulse response (FIR) and infinite-impulse-response (IIR) digital are presented. The FIR filter structure is optimized in the sense that for a given clock rate, both the utilization efficiency and average throughput are maximized. The IIR filter structure has approximately the same utilization efficiency and throughput rate as previous related techniques for processing a single data stream (channel), but it allows two data streams to be processed concurrently to double the performance. This feature makes the IIR system attractive for use in applications where multiple filtering and particularly bandpass analysis are required View full abstract»

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  • A line terminating LSI using echo cancelling method for ISDN subscriber loop transition

    Publication Year: 1988 , Page(s): 476 - 483
    Cited by:  Papers (1)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB)  

    A 144-kb/s digital subscriber loop (DSL) transmission system based on hybrid transmission with an echo cancelling method is described. It incorporates advanced LSI technology to obtain compactness, low cost, and high reliability. An echo canceller (EC) LSI has been developed using CMOS technology. Combined with the multiplexing processor (MXP) LSI, the EC LSI provides basic DSL equipment functions. A specially arranged frame format with a newly developed digital phase-locked loop (DPLL) circuit for stable timing extraction, an automatic balancing network, and a two-stage echo canceller characterize the system. Using this line termination circuit, the DSL equipment showed a reach of over 6 km when used with 0.5 mm diameter cable for 160-kb/s bidirectional digital transmission View full abstract»

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Aims & Scope

IEEE Journal on Selected Areas in Communications focuses on all telecommunications, including telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation.

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Editor-in-Chief
Muriel Médard
MIT