IEEE Transactions on Computers

Issue 9 • Sept. 1996

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Displaying Results 1 - 13 of 13
  • 2-1 addition and related arithmetic operations with threshold logic

    Publication Year: 1996, Page(s):1062 - 1067
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (655 KB)

    In this paper we investigate the reduction of the size for small depth feed-forward linear threshold networks performing binary addition and related functions. For n bit operands we propose a depth-3 O(n/sup 2//log n) asymptotic size network for the binary addition with O polynomially bounded weights. We propose also a depth-3 addition of optimal O(n) asymptotic sits network and a depth-2 comparis... View full abstract»

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  • Sigmoid generators for neural computing using piecewise approximations

    Publication Year: 1996, Page(s):1045 - 1049
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    A piecewise second order approximation scheme is proposed for computing the sigmoid function. The scheme provides high performance with low implementation cost; thus, it is suitable for hardwired cost effective neural emulators. It is shown that an implementation of the sigmoid generator outperforms, in both precision and speed, existing schemes using a bit serial pipelined implementation. The pro... View full abstract»

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  • CAA decoder for cellular automata based byte error correcting code

    Publication Year: 1996, Page(s):1003 - 1016
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1200 KB)

    The design of a cellular automata (CA) based byte error correcting code analogous to an extended Reed-Solomon code has been proposed by Chowdhury et al. (1982, 1985). This code has the same restrictions on error correction as that of an extended R-S code. A new design scheme has been reported for parallel implementation of the CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventi... View full abstract»

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  • Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry

    Publication Year: 1996, Page(s):1031 - 1044
    Cited by:  Papers (36)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1584 KB)

    Phased logic is proposed as a solution to the increasing problem of timing complexity in digital design. It is a delay-insensitive design methodology that seeks to restore the separation between logical and physical design by eliminating the need to distribute low-skew clock signals and carefully balance propagation delays. However, unlike other methodologies that avoid clocks, phased logic suppor... View full abstract»

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  • Improving the variable ordering of OBDDs is NP-complete

    Publication Year: 1996, Page(s):993 - 1002
    Cited by:  Papers (173)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    Ordered binary decision diagrams are a useful representation of Boolean functions, if a good variable ordering is known. Variable orderings are computed by heuristic algorithms and then improved with local search and simulated annealing algorithms. This approach is based on the conjecture that the following problem is NP-complete. Given an OBDD G representing f and a size bound s, does there exist... View full abstract»

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  • A hyper optimal encoding scheme for self-checking circuits

    Publication Year: 1996, Page(s):1022 - 1030
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    A typical self-checking circuit has an unordered code encoded output. The optimal scheme needs [log(r+1)] check bits, where r is the number of unique weights in all output patterns. A hyper optimal scheme for self-checking output encoding is proposed in this paper where the number of check bits will be further reduced in some cases. Two algorithms are presented to search for the hidden m-out-of-n ... View full abstract»

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  • Generalized partially-mixed-polarity Reed-Muller expansion and its fast computation

    Publication Year: 1996, Page(s):1084 - 1088
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    Generalized partially-mixed-polarity Reed-Muller (GPMPRM) expansion, a canonical subfamily of exclusive sum of products (ESOP), is presented. An efficient algorithm in two-dimensional data flow is proposed for computation of the GPMPRM forms. MCNC benchmark experimental results show that the minimal GPMPRM forms of these functions, on the average, have similar number of terms to their sum of produ... View full abstract»

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  • Dynamic prioritized conflict resolution on multiple access broadcast networks

    Publication Year: 1996, Page(s):1074 - 1079
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    In a multiple access broadcast network, all network nodes share a single shared communication channel, and there is the possibility of a collision when two or more nodes transmit at overlapping times. We propose a dynamic prioritized conflict resolution algorithm in which, when a collision occurs, all colliding messages are retransmitted according to their priority. When a new message arrives, it ... View full abstract»

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  • Carry-save multiplication schemes without final addition

    Publication Year: 1996, Page(s):1050 - 1055
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    Carry-save multipliers require an adder at the last step to convert the carry-sum representation of the most significant half of the result into a non-redundant form. This paper presents n×n multiplication schemes where this conversion is performed with a circuit operating in parallel with the carry-save array. The most relevant feature of the proposed multipliers is that the full 2n-bit res... View full abstract»

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  • Switching codes for delta-I noise reduction

    Publication Year: 1996, Page(s):1017 - 1021
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    In this paper, we address the off-chip driver delta-I or switching noise problem. We propose a novel approach based on switching codes to reduce this noise. These codes are designed to lower the number of drivers which switch in any given system cycle. A formal theoretic framework for switching codes is developed which provides an upper bound on the number of switching drivers as a function of bit... View full abstract»

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  • A multiple-sequence generator based on inverted nonlinear autonomous machines

    Publication Year: 1996, Page(s):1079 - 1083
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    A new multiple-sequence generator scheme to generate a set of deterministic ordered sequence of patterns followed by random patterns is presented in this paper. This scheme is based on an inverted nonlinear autonomous machine which utilizes a two-dimension-like LFSR with nonlinear inverters. A systematic procedure is also presented to obtain the autonomous machine which is more regular in the stru... View full abstract»

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  • Routing and transmitting problems in de Bruijn networks

    Publication Year: 1996, Page(s):1056 - 1062
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    De Bruijn graphs, both directed and undirected, have received considerable attention as architecture for interconnection networks. In this paper, we focus on undirected de Bruijn networks of radix d and dimension 0, denoted by UB(d, 0). We first discuss the shortest-path routing problem. We present properties of the shortest paths between any two vertices of UB(d, 0) and propose two shortest-path ... View full abstract»

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  • Unified mixed radix 2-4 redundant CORDIC processor

    Publication Year: 1996, Page(s):1068 - 1073
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    We present a unified mixed radix CORDIC algorithm with carry-save arithmetic with a constant scale factor. The pipelined architecture of the processor is determined by a unique sequence of microrotations for the two modes of operation (rotation and vectoring) in circular and hyperbolic coordinates. The combination of radix-2 and radix-4 microrotations allows us to reduce the latency and size of th... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org