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IEE Proceedings - Circuits, Devices and Systems

Issue 4 • Date Aug 1996

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Displaying Results 1 - 11 of 11
  • Multiphase AC-DC conversion by means of loss-free resistive networks

    Publication Year: 1996, Page(s):233 - 240
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (780 KB)

    Based on the loss-free resistor concept, a model of a network which enables ideal AC-DC conversion (zero line harmonics, unity power factor, nonpulsating output DC) is derived. Such a conversion unit has a hyperbolic output characteristic, which enables it to be operated with a variety of loads, and makes it suitable to be operated as a basic building block in modular systems. This approach has be... View full abstract»

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  • Backpropagation without multiplier for multilayer neural networks

    Publication Year: 1996, Page(s):229 - 232
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (408 KB)

    When multilayer neural networks are implemented with digital hardware, which allows full exploitation of the well developed digital VLSI technologies, the multiply operations in each neuron between the weights and the inputs can create a bottleneck in the system, because the digital multipliers are very demanding in terms of time or chip area. For this reason, the use of weights constrained to be ... View full abstract»

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  • Parallel event-driven logic simulation algorithms: tutorial and comparative evaluation

    Publication Year: 1996, Page(s):177 - 185
    Cited by:  Papers (1)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1020 KB)

    Parallel processing offers a viable way to improve the enormous execution time of the simulation of large VLSI designs. Various parallel logic simulation approaches have been proposed in recent years resulting in some ambiguity as to which scheme offers the best parallelism and execution time. To address these issues, the authors provide a detailed comparison of all four major types of event-drive... View full abstract»

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  • Dual topological theorems of linear active networks

    Publication Year: 1996, Page(s):225 - 228
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (284 KB)

    It is shown that in a network with current-controlled voltage sources the sum of the products of the impedances of the tree branches and their driving-point admittances plus the sum of the products of the controlling parameters of the current-controlled voltage sources and their associated transfer admittances equals the sum of the products of the admittances of the co-tree links and their driving... View full abstract»

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  • Input impedance and output impedance of feedback amplifiers

    Publication Year: 1996, Page(s):195 - 201
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (492 KB)

    A simple and precise method is given for calculating the input and output impedances of a feedback amplifier, directly from its loop gain. A useful approximation to the precise result is that the input or output impedance is equal to the source or load impedance for which loop gain would equal unity View full abstract»

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  • Precise insensitive current-mode third-order lowpass Butterworth characteristics

    Publication Year: 1996, Page(s):223 - 224
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (112 KB)

    The realisation of third-order lowpass Butterworth characteristics in the current mode using second-generation current conveyor (CC II) elements is presented. With nonideal CC IIs the denominator coefficients are altered slightly, which can be precisely compensated by suitable design. The network parameters are practically active-insensitive View full abstract»

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  • Design method for impedance matching networks

    Publication Year: 1996, Page(s):186 - 194
    Cited by:  Papers (14)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (888 KB)

    The design of basic passive LC networks, with particular attention to the ubiquitous II network, is studied for conjugate matching any two impedances and meeting a specified loaded quality factor Q0. Algebraic design formulae are analytically demonstrated, which prove extremely simple. Explicit expressions of network frequency responses and harmonic rejection in terms of the loaded Q... View full abstract»

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  • Semi-empirical model of electron mobility in MOSFETS in strong inversion regime

    Publication Year: 1996, Page(s):202 - 206
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (428 KB)

    The authors present a semi-empirical model for the electron mobility in a MOSFET in the strong inversion region. The model includes the contribution of the coulomb, phonon and surface-roughness scattering, and reproduces experimental results with high accuracy in the 77-300 K temperature range. The authors analyse the influence of coulomb scattering on the different terms of the model after stress... View full abstract»

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  • Parallel event-driven MOS timing simulator on distributed memory multiprocessors

    Publication Year: 1996, Page(s):207 - 212
    Cited by:  Papers (1)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (600 KB)

    PMOTA, a parallel event-driven relaxation-based timing simulator of MOS circuits on distributed memory multiprocessors, is proposed. Two new schemes, one a static data distribution and dynamic event assignment, the other a global synchronism local asynchronism scheme, are derived to reduce the communication overhead and achieve high speedup ratio, high processor utilisation, and balanced load amon... View full abstract»

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  • Design assistant approach to analogue layout generation

    Publication Year: 1996, Page(s):213 - 217
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (604 KB)

    The authors describe a novel analogue layout design assistant ALDA built around an industry-standard commercial CAD framework (CADENCE). The framework is used for the management of the design data and to provide access to low-level tools for tasks such as routing and compaction. This approach enables effort to be concentrated on the control of these tools and on addressing the specific issues and ... View full abstract»

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  • Current-mode ladder filters using multiple output current conveyors

    Publication Year: 1996, Page(s):218 - 222
    Cited by:  Papers (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (380 KB)

    A methodology to design continuous-time current-mode filters using current conveyors is presented. A multiple output current conveyor (MOCC), which contains both the positive and the negative outputs, is introduced. Based on the simulation of the passive RLC ladder prototypes, current-mode ladder filters using MOCCs are obtained. Designs show that the MOCC-based circuits can reduce the number of a... View full abstract»

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