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Circuits, Devices and Systems, IEE Proceedings -

Issue 4 • Date Aug 1996

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Displaying Results 1 - 11 of 11
  • Design method for impedance matching networks

    Page(s): 186 - 194
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    The design of basic passive LC networks, with particular attention to the ubiquitous II network, is studied for conjugate matching any two impedances and meeting a specified loaded quality factor Q0. Algebraic design formulae are analytically demonstrated, which prove extremely simple. Explicit expressions of network frequency responses and harmonic rejection in terms of the loaded Q0 and the given impedances are established and a method for determining the loaded Q0 for any required harmonic attenuation is developed. The authors formulate and discuss all tolerance and parasitic sensitivities and their relation to the loaded Q0. The design method is also presented from the power transmission viewpoint. In particular, actual power transmission relations, taking the finite unloaded Qu into account, are derived in terms of the loaded and unloaded Q. The authors also address the design problem with regard to the standing wave ratio and reflection coefficient. Using the relations derived we can achieve both the maximum power transfer and the required harmonic rejection at any frequencies precisely, and we can also readily evaluate and incorporate other performances, View full abstract»

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  • Input impedance and output impedance of feedback amplifiers

    Page(s): 195 - 201
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    A simple and precise method is given for calculating the input and output impedances of a feedback amplifier, directly from its loop gain. A useful approximation to the precise result is that the input or output impedance is equal to the source or load impedance for which loop gain would equal unity View full abstract»

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  • Parallel event-driven MOS timing simulator on distributed memory multiprocessors

    Page(s): 207 - 212
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    PMOTA, a parallel event-driven relaxation-based timing simulator of MOS circuits on distributed memory multiprocessors, is proposed. Two new schemes, one a static data distribution and dynamic event assignment, the other a global synchronism local asynchronism scheme, are derived to reduce the communication overhead and achieve high speedup ratio, high processor utilisation, and balanced load among processor elements. Implementation results show that parallel simulations on a distributed memory multiprocessor are feasible for large-scale circuit simulation View full abstract»

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  • Parallel event-driven logic simulation algorithms: tutorial and comparative evaluation

    Page(s): 177 - 185
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1020 KB)  

    Parallel processing offers a viable way to improve the enormous execution time of the simulation of large VLSI designs. Various parallel logic simulation approaches have been proposed in recent years resulting in some ambiguity as to which scheme offers the best parallelism and execution time. To address these issues, the authors provide a detailed comparison of all four major types of event-driven logic simulation algorithms (synchronous, conservative asynchronous with deadlock avoidance, conservative asynchronous with deadlock detection and resolution, and optimistic asynchronous). The comparisons are carried out on an ideal parallel machine capable of extracting all available parallelism in a given algorithm. The simulation execution time, average parallelism and total messages required for a particular simulation algorithm are measured on the ISCAS combinational and sequential benchmark circuits. The use of an ideal parallel machine exposes characteristics of the simulation algorithms independent of the effects caused by particular parallel architectures or implementations. It is shown that a recently developed conservative asynchronous algorithm of the deadlock avoidance type and the optimistic asynchronous algorithm achieve the best parallel execution time results. However, the new conservative algorithm requires much less implementation overhead than the optimistic algorithm View full abstract»

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  • Semi-empirical model of electron mobility in MOSFETS in strong inversion regime

    Page(s): 202 - 206
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    The authors present a semi-empirical model for the electron mobility in a MOSFET in the strong inversion region. The model includes the contribution of the coulomb, phonon and surface-roughness scattering, and reproduces experimental results with high accuracy in the 77-300 K temperature range. The authors analyse the influence of coulomb scattering on the different terms of the model after stressing the samples with successive Fowler-Nordheim tunnelling-injection series. In addition, it is shown that the terms a priori attributed to coulomb and phonon scattering receive the contribution of both mechanisms and thus cannot be separately attributed to each of them View full abstract»

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  • Design assistant approach to analogue layout generation

    Page(s): 213 - 217
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    The authors describe a novel analogue layout design assistant ALDA built around an industry-standard commercial CAD framework (CADENCE). The framework is used for the management of the design data and to provide access to low-level tools for tasks such as routing and compaction. This approach enables effort to be concentrated on the control of these tools and on addressing the specific issues and problems related to analogue layout. The approach adopted in ALDA involves a floorplanning phase, followed by a detailed physical assembly phase. The floorplan is hierarchical and is driven by constraints specified by the user; the placement within each hierarchical group is based on an objective function reflecting both interconnect efficiency and silicon usage. Physical assembly is carried out in a nested, bottom-up, sequence of place-route-compact operations, following the hierarchical floorplan structure. ALDA achieves this by defining a placement in the framework's layout database and then controlling the framework's router and compactor to generate the detailed layout of each group in the hierarchy. ALDA's operation is illustrated with the design of a 61 component CMOS op-amp, which is representative of a typical industrial design View full abstract»

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  • Dual topological theorems of linear active networks

    Page(s): 225 - 228
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    It is shown that in a network with current-controlled voltage sources the sum of the products of the impedances of the tree branches and their driving-point admittances plus the sum of the products of the controlling parameters of the current-controlled voltage sources and their associated transfer admittances equals the sum of the products of the admittances of the co-tree links and their driving-point impedances. In a network with voltage-controlled current sources (VCCS), the sum of the products of the admittances of co-tree links and their driving-point impedances plus the sum of the products of the controlling parameters of the VCCS and their associated transfer impedances equals the sum of the products of the impedances of tree branches and their driving-point admittances View full abstract»

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  • Precise insensitive current-mode third-order lowpass Butterworth characteristics

    Page(s): 223 - 224
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    The realisation of third-order lowpass Butterworth characteristics in the current mode using second-generation current conveyor (CC II) elements is presented. With nonideal CC IIs the denominator coefficients are altered slightly, which can be precisely compensated by suitable design. The network parameters are practically active-insensitive View full abstract»

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  • Current-mode ladder filters using multiple output current conveyors

    Page(s): 218 - 222
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    A methodology to design continuous-time current-mode filters using current conveyors is presented. A multiple output current conveyor (MOCC), which contains both the positive and the negative outputs, is introduced. Based on the simulation of the passive RLC ladder prototypes, current-mode ladder filters using MOCCs are obtained. Designs show that the MOCC-based circuits can reduce the number of active components by 50%. A fifth-order all-pole lowpass ladder filter, with 1 MHz passband frequency, 0.5dB ripple, and a third-order elliptic lowpass ladder filter, with 2.4 MHz passband frequency and 0.1773 dB ripple, are designed and simulated View full abstract»

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  • Multiphase AC-DC conversion by means of loss-free resistive networks

    Page(s): 233 - 240
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (780 KB)  

    Based on the loss-free resistor concept, a model of a network which enables ideal AC-DC conversion (zero line harmonics, unity power factor, nonpulsating output DC) is derived. Such a conversion unit has a hyperbolic output characteristic, which enables it to be operated with a variety of loads, and makes it suitable to be operated as a basic building block in modular systems. This approach has been verified experimentally, by the construction of a high quality three-phase AC-DC converter, based on three flyback circuits that realised the loss-free resistors View full abstract»

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  • Backpropagation without multiplier for multilayer neural networks

    Page(s): 229 - 232
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    When multilayer neural networks are implemented with digital hardware, which allows full exploitation of the well developed digital VLSI technologies, the multiply operations in each neuron between the weights and the inputs can create a bottleneck in the system, because the digital multipliers are very demanding in terms of time or chip area. For this reason, the use of weights constrained to be power-of-two has been proposed in the paper to reduce the computational requirements of the networks. In this case, because one of the two multiplier operands is a power-of-two, the multiple operation can be performed as a much simpler shift operation on the neuron input. While this approach greatly reduces the computational burden of the forward phase of the network, the learning phase, performed using the traditional backpropagation procedure, still requires many regular multiplications. In the paper, a new learning procedure, based on the power-of-two approach, is proposed that can be performed using only shift and add operations, so that both the forward and learning phases of the network can be easily implemented with digital hardware View full abstract»

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