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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct 1996

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Displaying Results 1 - 18 of 18
  • High-mobility strained-Si PMOSFET's

    Page(s): 1709 - 1716
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    Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si0.82Ge0.18 buffer layer on Si(100) substrate. At high vertical fields (high |Vg|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO2 interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K View full abstract»

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  • Silicon carbide high-power devices

    Page(s): 1732 - 1741
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    In recent years, silicon carbide has received increased attention because of its potential for high-power devices. The unique material properties of SiC, high electric breakdown field, high saturated electron drift velocity, and high thermal conductivity are what give this material its tremendous potential in the power device arena. 4H-SiC Schottky barrier diodes (1400 V) with forward current densities over 700 A/cm2 at 2 V have been demonstrated. Packaged SITs have produced 57 W of output power at 500 MHz, SiC UMOSFETs (1200 V) are projected to have 15 times the current density of Si IGBTs (1200 V). Submicron gate length 4H-SiC MESFETs have achieved fmax=32 GHz, fT=14.0 GHz, and power density=2.8 W/mm @ 1.8 GHz. The performances of a wide variety of SiC devices are compared to that of similar Si and GaAs devices and to theoretically expected results View full abstract»

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  • Integrated Systems [systems on a chip]

    Page(s): 1678 - 1687
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    Integrated Systems are defined as batch-fabricated interconnections of complex digital integrated circuits with analog interface circuits and transducers, such as sensors. By providing the cost, performance and reliability levels of monolithic integration, they offer potential advantages over multi-chip modules assembled with packaging technology. This paper studies the required process technology, as well as design, test and packaging issues, for integrating wide varieties of systems. The goal is to delineate the necessary steps in bringing Integrated Systems to market within a realistic period. With monolithic integration as the ultimate aim, a multi-chip entry point is identified that can start system technology on a learning curve of cost reduction using the same scaling principles that drive integrated circuits. Three challenges to be surmounted are identified in streamlining the I/O's and progressing along a learning curve, namely I/O scaling, I/O loading, and full-functional test. The “composite IC” is the entry point. A large chip, containing only global interconnects and power distribution, acts as a silicon backplane. Subsystem-chips, such as digital microprocessors or sensors, are flip-chip mounted using the accuracy of MEMS processing to fabricate “snap-together” physical and electrical interfaces with high reproducibility. While similar to conventional MCM's, this chip-to-chip connection has few compromises over on-chip connections. By keeping the fabrication responsibility within one organization, just as in monolithic chips, there is no need for incoming inspection. Added ESD protection and test-head loading are avoided on interior nodes by a new intra-factory method of testing View full abstract»

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  • Wide bandgap semiconductor materials and devices

    Page(s): 1633 - 1636
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    Given a matrix of all semiconductor materials and their properties, the highest and the lowest of these property values will almost always be associated with wide bandgap materials. The many possible combinations of these “poles and zeros” lead not only to superlative electron device performance, but to new device concepts as well. An overview of wide bandgap semiconductor properties is presented followed by several concepts for both new and enhanced devices. Finally, impediments to immediate exploitation and a time-oriented appraisal of the various materials and devices is presented View full abstract»

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  • Plasma wave electronics: novel terahertz devices using two dimensional electron fluid

    Page(s): 1640 - 1645
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    We discuss how the propagation of plasma waves in a High Electron Mobility Transistor (HEMT) can be used to implement a new generation of terahertz devices, including sources, resonant detectors, broad band detectors, and frequency multipliers. Our estimates show that these devices should outperform conventional terahertz devices, which use deep submicron Schottky diodes View full abstract»

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  • Functional devices based on real space transfer in Si/SiGe structure

    Page(s): 1671 - 1677
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    A charge injection transistor, which operates as an exclusive-OR logic gate, and a monolithic multiterminal device, electrically reprogrammable between OR and NAND logic function, have been successfully implemented in a Si-Si0.7Ge0.3 heterostructure grown by rapid thermal epitaxy on a Si substrate. Room temperature operation of the charge injection transistor is demonstrated, with 10 dB on/off ratio for the exclusive-OR logic function. Microwave measurements indicate a short circuit current gain cutoff of 6 GHz, for a device with a source-drain distance of 0.5 μm. Device simulations were used to identify primary dependencies of the device performance on the parameters used in the design of the structure. Further structural improvements are suggested View full abstract»

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  • On the application of the Neuron MOS transistor principle for modern VLSI design

    Page(s): 1700 - 1708
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    In this paper, the speed performance, power consumption, and layout area of Neuron MOS transistor circuits are monitored considering the requirements of modern VLSI design. The Neuron MOS transistor is a recently discovered device principle which has a number of input gates that couple capacitively to a floating gate. The floating gate potential controls the current of a transistor channel. This device can be used in logic circuits. A threshold current through the Neuron MOS transistor can be defined that causes a switching of the output of the logic circuits as soon as the channel current surmounts or falls below the specified value. We designed two different multiplier cells, one based on a Neuron MOS inverter, and the other on a Neuron MOS n-MOSFET which is used as one input device of a comparator circuit. Functionality of both cells is proven for data rates up to 50 MHz which represents the first high-speed measurement of a circuit based on this new design principle. A perspective for the upper speed limit found at more than 500 MHz is given by simulation. The new design principle has a layout area reduced by more than a factor of two compared to usual multiplier cells. Moreover, it is shown, that depending on the design chosen, high speed operation leads to considerable power savings. In view of those advantages it is concluded that the principle of threshold logic qualifies for a major breakthrough for packing density improvement of CMOS-based applications View full abstract»

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  • Quantum-well Hall devices in Si-delta-doped Al0.25Ga0.75As/GaAs and pseudomorphic Al0.25 Ga0.75As/In0.25Ga0.75As/GaAs heterostructures grown by LP-MOCVD: performance comparisons

    Page(s): 1665 - 1670
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    Characterized herein are quantum-well Hall devices in Si-delta-doped Al0.25Ga0.75As/GaAs and pseudomorphic Al0.25Ga0.75As/In0.25Ga 0.75As/GaAs heterostructures, grown by low-pressure metal organic chemical vapor deposition method. The Si-delta-doping technique has been applied to quantum-well Hall devices for the first time. As a result high electron mobilities of 8100 cm-2/V·s with a sheet electron density of 1.5×1012 cm-2 in Al0.25Ga0.75As/In0.25Ga0.75 As/GaAs structure and of 6000 cm-2/V·s with the sheet electron density of 1.2×1012 cm-2 in Al0.25Ga0.75As/GaAs structure have been achieved at room temperature, respectively. From Hall devices in Al0.25Ga0.75As/In0.25Ga0.75 As structure, the product sensitivity of 420 V/AT with temperature coefficient of -0.015 %/K has been obtained. This temperature characteristic is one of the best result reported. Additionally, a high signal-to-noise ratio corresponding to the minimum detectable magnetic field of 45 nT at 1 kHz and 75 nT at 100 Hz has been attained. These resolutions are among the best reported results View full abstract»

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  • Trends in power semiconductor devices

    Page(s): 1717 - 1731
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    This paper reviews recent trends in power semiconductor device technology that are leading to improvements in power losses for power electronic systems. In the case of low voltage (<100 V) power rectifiers, the silicon P-i-N rectifier has been displaced by the silicon Schottky rectifier, and it is projected that the silicon TMBS rectifier will be the preferred choice in the future. In the case of high voltage (>100 V) power rectifiers, the silicon P-i-N rectifier continues to dominate but significant improvements are expected by the introduction of the silicon MPS rectifier followed by the GaAs and SiC based Schottky rectifiers. Equally important developments are occurring in power switch technology. The silicon bipolar power transistor has been displaced by silicon power MOSFETs in low voltage (<100 V) systems and by the silicon IGBTs in high voltage (>100 V) systems. The process technology for these MOS-gated devices has shifted from V-MOS in the early 1970s to DMOS in the 1980s, with more recent introduction of the UMOS technology in the 1990s. For the very high power systems, the thyristor and GTO continue to dominate, but significant effort is underway to develop MOS-gated thyristors (MCTs, ESTs, DG-BRTs) to replace them before the turn of the century. Beyond that time frame, it is projected that silicon carbide based switches will begin to displace these silicon devices View full abstract»

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  • Lithography-independent nanometer silicon MOSFETs on insulator

    Page(s): 1626 - 1632
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    Future field-effect transistors should have control regions-also called channels or barriers-of a few tens of nanometers to achieve a transconductance of 1 Siemens per mm and beyond, fT of 100 GHz and safe operating voltages beyond 1 V. This paper presents two approaches for the fabrication of such MOS transistors in silicon on insulator (SOI) on today's average technology lines without resorting to nanometer lithography, but rather using differential doping available in reduced temperature epitaxy and implantation. With 6 nm oxinitride gate dielectrics, inner transconductances of 700 mS/mm at room temperature are reported View full abstract»

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  • Need for critical assessment

    Page(s): 1637 - 1639
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    Adventurous technological proposals are subject to inadequate critical assessment. It is the proponents who organize meetings and special issues. Optical logic, mesoscopic switching devices and quantum parallelism are used to illustrate this problem View full abstract»

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  • A comparative study of advanced MOSFET concepts

    Page(s): 1742 - 1753
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    Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been the major device for integrated circuits over the past two decades. With technology advancement, there have been numerous MOSFET structures for channel length of 0.1 μm and below reported in industrial research. A side-by-side comparison of these advanced device structures can provide useful understanding in device physics and the design tradeoffs among MOSFET's parameters. In this work we employ experimental data, device simulation, and analytical modeling for device comparison. The devices were developed at several different research laboratories. Guided by experimental data and simulations, analytical models for topics such as threshold voltage, short-channel effect, and saturation current for these different MOSFET structures are developed. These analytical models are then used for optimizing each device structure and comparing the devices under the same set of constraints for a fair comparison. The key design parameters are highlighted and the strength and weakness of each device structure in various performance categories are discussed View full abstract»

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  • Collective computational activity in self-assembled arrays of quantum dots: a novel neuromorphic architecture for nanoelectronics

    Page(s): 1688 - 1699
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    We describe a new class of nanoelectronic circuits which exploits the charging behavior in resistively/capacitively linked arrays of nanometer-sized metallic islands (quantum dots), self-assembled on a resonant tunneling diode, to perform neuromorphic computation. These circuits produce associative memory effects and realize the additive short-term memory (STM) or content addressable memory (CAM) models of neural networks without requiring either large-area/high-power operational amplifiers, or massive interconnectivity between devices. Both these requirements had seriously hindered the application of neural networks in the past. Additionally, the circuits can solve NP-complete optimization problems (such as the traveling salesman problem) using single electron charge dynamics, exhibit rudimentary image-processing capability, and operate at room temperature unlike most quantum devices. Two-dimensional (2D) processors, with a 100×100 pixel capacity, can be fabricated in an area of 10-8 cm2 leading to unprecedented functional density. Possible routes to synthesizing these circuits, employing self-assembly, are also discussed View full abstract»

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  • Application of quantum-based devices: trends and challenges

    Page(s): 1621 - 1625
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    Revolutionary nanofabrication techniques and trends have opened the way to fabricating quantum wells, quantum wires and quantum dots that may provide the basic building blocks for future nanoelectronic and mesoscopic (quantum) device technologies. Furthermore, these trends lead to new opportunities for realizing quantum-based information processing devices but many challenges must be addressed and intensive international basic research is essential for the full exploitation of these revolutionary devices View full abstract»

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  • A survey of semiconductor devices

    Page(s): 1760 - 1766
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    This paper attempts to present a complete collection of semiconductor devices. A total of 67 “major” devices have been identified, together with about 110 device variations which are considered to be “related” devices to the former. These devices are organized into groups and subgroups for a better overview, and the justification for such classification is discussed. After the list is presented, the author offers some comments and observations from his viewpoint View full abstract»

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  • A mesoscopic ballistic electron mixer with efficient frequency conversion at radio frequency

    Page(s): 1754 - 1759
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    The voltage-current characteristic of a four-terminal mesoscopic cross is grossly nonlinear, exhibiting two clear regions of negative differential resistance (NDR). This behavior is potentially useful in millimeter wave detectors since these small devices have very low parasitic capacitance and great sensitivity. The device exploits a planar GaAs technology which lends itself to integrated systems. We have exploited one of the NDR regions (at a current of only 1.9 μA) to carry out frequency conversion. At low frequency we observed efficient frequency doubling, with the second harmonic exceeding the fundamental by up to 10 dB at the output. We have also operated the device at radio frequency (5 MHz) and demonstrated both asynchronous and heterodyne amplitude demodulation. The effect of DC current bias was examined and it was shown that biasing the device close to the NDR gave the optimum frequency conversion. A conversion loss in the heterodyne mixer circuit of 3 dB was achieved View full abstract»

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  • GaInP/InGaAs/GaAs graded barrier MODFET grown by OMVPE: design, fabrication, and device results

    Page(s): 1659 - 1664
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    GaxIn1-xP/GayIn1-x As/GaAs Modulation Doped Field Effect Transistors (MODFET's) with a pseudomorphic barrier and a pseudomorphic channel were grown by Organo Metallic Vapor Phase Epitaxy (OMVPE). This material system is promising for advanced MODFET's on GaAs for high frequency and power applications, because of the large discontinuity in the conduction band, advantages in the processing and the capability to increase the energy separation between the bottom of the conduction band and Fermi level by compositionally grading the barriers. Record 2-dimensional Electron Gas (2-DEG) carrier densities of 3.1·1012 cm-2 for single-sided MODFET's were measured. Measured RF power at 10 GHz for 0.25 pm devices was ⩾0.4 W/mm. For the first time cutoff frequencies fT and fmax exceeding 105 and 188 GHz, respectively, were obtained for this material system with 0.1 μm gate-length MODFET's View full abstract»

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  • Nonlithographic nano-wire arrays: fabrication, physics, and device applications

    Page(s): 1646 - 1658
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    A novel system of nanostructures is described consisting of nonlithographically produced arrays of nano-wires directly electrodeposited into porous anodic aluminum oxide templates. Using this method regular and uniform arrays of metal or semiconductor nano-wires or nano-dots can be created with diameters ranging from ~5 nm to several hundred nanometers and with areal pore densities in the ~109-1011 cm-2 range. We report on the present state of their fabrication, properties, and prospective device applications. Results of X-ray diffraction, Raman and magnetic measurements on metal (Ni, Fe) and semiconductor (CdS, CdSe, CdSx Se1-x, CdxZn1-xS and GaAs) wires are presented. The I-V characteristics of two terminal devices made from the nano-arrays are found to exhibit room temperature periodic conductance oscillations and Coulomb-blockade like current staircases. These observations are likely associated with the ultra-small tunnel junctions that are formed naturally in the arrays. Single-electron tunneling (SET) In the presence of interwire coupling in these arrays is shown to lead to the spontaneous electrostatic polarization of the wires. Possible device applications such as magnetic memory or sensors, electroluminescent flat-panel displays, and nanoelectronic and single-electronic devices are also discussed View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

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Dept. ECE
University of California San Diego