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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 9 • Date Sep 1996

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Displaying Results 1 - 7 of 7
  • Exchange algorithms for the design of linear phase FIR filters and differentiators having flat monotonic passbands and equiripple stopbands

    Page(s): 671 - 675
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    The authors describe a modification of a technique proposed by Vaidyanathan (1985) for the design of filters having flat passbands and equiripple stopbands. The modification ensures that the passband is monotonic and does so without the use of concavity constraints. Another modification described in this brief adapts the method of Vaidyanathan to the design of low-pass differentiators having a specified degree of tangency at ω=0 View full abstract»

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  • Structure generation of current-mode two integrator loop dual output-OTA grounded capacitor filters

    Page(s): 659 - 663
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    A variety of new current-mode continuous-time two integrator loop filter architectures incorporating dual output operational transconductance amplifiers (DO-OTA) and capacitors (C) are generated. These DO-OTA-C configurations consist of 2-6 DO-OTAs, depending on the structure and only 2 grounded capacitors. They are convenient for integration, suitable for high frequency, multifunctional, electronically tunable, of low sensitivity, simple in structure and easy to design. The selection of the filter structure and effects of DO-OTA nonidealities are discussed View full abstract»

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  • Split Recursive Least-Squares: algorithms, architectures, and applications

    Page(s): 645 - 658
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1284 KB)  

    In this paper, a new computationally efficient algorithm for adaptive filtering is presented. The proposed Split Recursive Least-Squares (Split RLS) algorithm can perform the approximated RLS with O(N) complexity for signals having no special data structure to be exploited (e.g., the signals in multichannel adaptive filtering applications, which are not shifts of a single-channel signal data), while avoiding the high computational complexity (O(N2)) required in the conventional RLS algorithms. Our performance analysis shows that the estimation bias will be small when the input data are less correlated. We also show that for highly correlated data, the orthogonal preprocessing scheme can be used to improve the performance of the Split RLS. Furthermore, the systolic implementation of our algorithm based on the QR-decomposition RLS (QRD-RLS) array as well as its application to multidimensional adaptive filtering is also discussed. The hardware complexity for the resulting array is only O(N) and the system latency can be reduced to O(log2 N). The simulation results show that the Split RLS outperforms the conventional RLS in the application of image restoration. A major advantage of the Split RLS is its superior tracking capability over the conventional RLS under nonstationary environments View full abstract»

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  • A novel CMOS current conveyor realization with an electronically tunable current mode filter suitable for VLSI

    Page(s): 663 - 670
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    A novel CMOS realization of the second generation current conveyor is given. A circuit which compensates the voltage offset due to channel length modulation effect is then developed. The CCII is then used to realize a new electronically tunable low-pass-band-pass filter suitable for VLSI. Simulation results taking the second-order effects into account indicate the excellent performance of both the CCII circuit and the filter over a wide dynamic range View full abstract»

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  • A fast convergence algorithm for adaptive FIR filters under computational constraint for adaptive tap-position control

    Page(s): 629 - 636
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    This paper proposes a fast convergence algorithm for adaptive FIR filters with tap-position control. The proposed algorithm consists of two stages: flat-delay estimation and constrained tap-position control. In the flat-delay estimation, the scattered coefficients are allowed to change their positions to achieve fast and correct flat-delay estimation. For constrained tap-position control, special attention is paid to a limit in computational power imposed by the hardware. By dividing a first-in-first-out queue into two parts, which store indexes to inactive taps with no assigned coefficient, fast convergence is achieved even when computation per sampling period for tap-position control is limited. Simulation results show that under the same computational limit as the conventional algorithm, the proposed algorithm reduces the convergence time by as much as 60%. The convergence speed remains unchanged for different computational limits. This algorithm is promising for echo cancellation in satellite links and in data transmission with modems View full abstract»

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  • Fast interpolation of n-dimensional signal by subsequence FFT

    Page(s): 675 - 676
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    Based on the differential property of Fourier transform and the Taylor expansion of a n-variables function, the subsequence interpolating algorithm is extended to a general n-dimensional signal. As the interpolating process is consisted of a few parallel inverse FFT with the same size as the forward FFT, it is very efficient and is suitable for parallel processing View full abstract»

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  • A new hardware-efficient architecture for programmable FIR filters

    Page(s): 637 - 644
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    Although much research has been done on efficient high-speed filter architectures, much of this work has focused on filters with fixed coefficients, such as Canonical Signed Digit coefficient filter architectures, multiplierless designs, or memory-based designs. In this paper, we focus on digit-serial, high-speed architectures with programmable coefficients. To achieve high performance goals, we consider both of algorithm level and architecture implementation level of FIR filters. In algorithm level, we reformulate the FIR formulation in bit-level and take the associative property of the addition in both the digit-serial multiplications and filter formulations. In architecture level, we considered issues to implement the reformulated results efficiently. The issues include addition implementation, data flow arrangements, and treatment of sign-extensions. Based on the above considerations, we can obtain a filter architecture with accumulation-free tap structure and properties of short latency, flexible pipelinability and high speed. Comparing the cost and performance with previous designs, we find that the proposed architecture reduces the hardware cost of a programmable FIR filter to only half that of previous designs without sacrificing performance View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

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