IEEE Transactions on Computers

Issue 8 • Aug 1996

Filter Results

Displaying Results 1 - 13 of 13
  • Optimal realization of sets of interconnection functions on synchronous multiple bus systems

    Publication Year: 1996, Page(s):964 - 969
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (644 KB)

    We develop a formal and systematic methodology for designing an optimal multiple bus system (MBS) realizing a set of interconnection functions whose graphical representation (denoted as IFG) is symmetric. The problem of constructing an optimal MBS for a given IFG is NP-hard. In this paper, we show that polynomial time solutions exist when the IFG is vertex symmetric. This is the case of interest f... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testability of convergent tree circuits

    Publication Year: 1996, Page(s):950 - 963
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1184 KB)

    The testing properties of a class of regular circuits called convergent trees are investigated. Convergent trees include such practical circuits as comparators, multiplexers, and carry-lookahead adders. The conditions for the testability of these tree circuits are derived for a functional fault model. The notion of L-testability is introduced, where the number of tests for a p-level tree is direct... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A methodology for the rapid injection of transient hardware errors

    Publication Year: 1996, Page(s):881 - 891
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1276 KB)

    Ultra-dependable computing demands verification of fault-tolerant mechanisms in the hardware. The most popular class of verification methodologies, fault-injection, is fraught with a host of limitations. Methods which are rapid enough to be feasible are not based on actual hardware faults. On the other hand, methods which are based on gate-level faults require enormous time resources. This researc... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Augmented binary hypercube: a new architecture for processor management

    Publication Year: 1996, Page(s):980 - 984
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (492 KB)

    Augmented Binary Hypercube (AH) architecture consists of the binary hypercube processor nodes (PNs) and a hierarchy of management nodes (MNs). Several distributed algorithms maintain subcube information at the MNs to realize fault tolerant, fragmentation free processor allocation and load balancing. For efficient implementation of AH, we map MNs onto PNs, define and prove infeasibility of ideal ma... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reducing the MISR size

    Publication Year: 1996, Page(s):930 - 938
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (896 KB)

    Multiple-input signature registers (MISRs) are commonly used in built-in self-test (BIST) applications. The size of the MISR is dictated by the number of signals it has to compress. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Large size MISRs pose problems in terms of hardware and... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A modified TRAM architecture

    Publication Year: 1996, Page(s):969 - 974
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (576 KB)

    This paper modifies the tree RAM (TRAM) architecture (Jarwala and Pradhan, 1988) of multimegabit dynamic random access memories using a tree-star (TS) interconnection topology. The modified TS-RAM design offers a reduced access time and an improved yield for the proposed TS-RAM architecture. We also propose an improved built-in self test (BIST) approach for the architecture View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On diagnosability of large fault sets in regular topology-based computer systems

    Publication Year: 1996, Page(s):892 - 903
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1208 KB)

    The classical diagnosability approach has its limitation when dealing with large fault sets in large multiprocessor systems. This is due to limited diagnosability of large multiprocessor systems connected using regular interconnection structures. We propose an alternative approach to system diagnosis by allowing a few upper bounded number of units to be diagnosed incorrectly. This measure is calle... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis of delay fault testability circuits

    Publication Year: 1996, Page(s):985 - 991
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (636 KB)

    Multilevel Logic Optimization Transformations used in existing logic synthesis systems are characterized with respect to their testability preserving and testability enhancing properties. A sufficient condition for a multilevel unate circuit to be “hazard free delay fault testable” is presented. In contrast to existing results that consider either “single path propagating hazard ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Arithmetic additive generators of pseudo-exhaustive test patterns

    Publication Year: 1996, Page(s):939 - 949
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1160 KB)

    Existing built-in self-test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose an entirely new approach to generate test patterns. The method is based on adders widely available in data-path architectures used in digital signal processing circuits and general purpose pro... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The effect of program behavior on fault observability

    Publication Year: 1996, Page(s):868 - 880
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1224 KB)

    Fault observability based on the behavior of memory references is studied. Traditional studies view memory as one monolithic entity that must completely work to be considered reliable. The usage patterns of a particular program's memory are emphasized here. This paper develops a new model for the successful execution of a program taking into account the usage of the data by extending a cache memor... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System dependability evaluation via a fault list generation algorithm

    Publication Year: 1996, Page(s):974 - 979
    Cited by:  Papers (11)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (640 KB)

    The size and complexity of modern dependable computing systems has significantly compromised the ability to accurately measure system dependability attributes such as fault coverage and fault latency. Fault injection is one approach for the evaluation of dependability metrics. Unfortunately, fault injection techniques are difficult to apply because the size of the fault set is essentially infinite... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On evaluating and optimizing weights for weighted random pattern testing

    Publication Year: 1996, Page(s):904 - 916
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1256 KB)

    Two problems in weighted random pattern testing are considered: 1) evaluating a set of input weights in terms of the amount of time required to generate a set of test patterns and 2) determining the optimal weights for a given test set. An exact expression for expected test length is derived as a function of input weights. Upper and lower bounds for expected test length are presented. Percentage e... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A sweeping line approach to interconnect testing

    Publication Year: 1996, Page(s):917 - 929
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1356 KB)

    This paper presents a new structural approach for test generation and diagnosis of interconnects (such as wiring networks). The proposed technique is based on computational geometry by considering the physical adjacencies of the nets in the layout. This information is used by a sweeping line technique for generating the test vectors. A realistic fault model in which nets can be bridged only if the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org