By Topic

IEE Proceedings - Computers and Digital Techniques

Issue 4 • Date Jul 1996

Filter Results

Displaying Results 1 - 7 of 7
  • Tabular techniques for generating Kronecker expansions

    Publication Year: 1996, Page(s):205 - 212
    Cited by:  Papers (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (732 KB)

    Tabular techniques and algorithms for generating Kronecker expansions are presented. The Kronecker expansions, a subclass of mixed-polarity Reed-Muller expansions, can be generated from Boolean functions Kronecker expansions of different polarity. The techniques can be used for completely and incompletely specified Boolean functions. The algorithms were implemented in Pascal and fully tested. Exam... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of a method of optimising data distribution on a loosely coupled multiprocessor system

    Publication Year: 1996, Page(s):239 - 245
    Cited by:  Papers (1)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (600 KB)

    The maximum speedup of a multiprocessor system is limited by the sequential part of an algorithm, and in loosely coupled processor systems a large part of this sequentiality is caused by the communication between processors. As this communication is dependent on the distribution of data the data distribution must be optimised in order to achieve the maximum speedup. In the paper the authors presen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Database of best T-codes

    Publication Year: 1996, Page(s):213 - 218
    Cited by:  Papers (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (680 KB)

    T-codes are variable-length codes that have been shown to provide excellent codeword synchronisation properties without any sacrifice in coding efficiency. Previously published results have used simulation techniques to ascertain the synchronising properties of each T-code. The author presents the first theoretical technique for calculating the synchronising delay of a T-code based on the code set... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Note on optimal tile partition for space region of integrated-circuit geometry

    Publication Year: 1996, Page(s):246 - 248
    Cited by:  Patents (13)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (308 KB)

    An OTP algorithm for solving the optimal tile-partitioning problem has recently been published by P.Y. Hsiao et al. (1993). The OTP algorithm makes use of an elimination algorithm to find a maximum set of nonintersecting critical partition edges. It is shown that this elimination algorithm is flawed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Speculative parallel simulated annealing with acceptance prediction

    Publication Year: 1996, Page(s):219 - 223
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (432 KB)

    In the paper, a novel problem-independent parallel realisation of the simulated annealing (SA) algorithm is proposed. By employing speculative computation, concurrency is introduced into the inherently sequential algorithm. This is achieved by predicting the acceptance of each generated move before the move is evaluated. Based on this prediction, subsequent moves can be proposed and evaluated befo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance-oriented synchronisation migration in a DOACROSS loop

    Publication Year: 1996, Page(s):224 - 231
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (760 KB)

    A statement-level migration of synchronisation operation for performance enhancement is proposed. Theorems show that system performance is enhanced if the number of array elements in the maximal backward synchronisation region is reduced. This task is divided into three steps. First the redundant statements are moved out of the maximal backward synchronisation region by dependence analysis. Second... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Area efficient systolic interconnection networks

    Publication Year: 1996, Page(s):232 - 238
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (832 KB)

    Area efficient VLSI design of interconnection networks is an important problem in multiprocessor design. In the context of ULSI technology, the delay in signal propagation along wires will become a significant limitation in designing large, fast networks. This limitation is particularly applicable for high wire organisations typically used in interconnection networks. In the paper, it is shown tha... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.