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Computers and Digital Techniques, IEE Proceedings -

Issue 4 • Date Jul 1996

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Displaying Results 1 - 7 of 7
  • Development of a method of optimising data distribution on a loosely coupled multiprocessor system

    Publication Year: 1996 , Page(s): 239 - 245
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    The maximum speedup of a multiprocessor system is limited by the sequential part of an algorithm, and in loosely coupled processor systems a large part of this sequentiality is caused by the communication between processors. As this communication is dependent on the distribution of data the data distribution must be optimised in order to achieve the maximum speedup. In the paper the authors present a new method of determining the distribution for loosely coupled multiprocessors using a branch and bound technique based on the Moore-Skelboe interval arithmetic algorithm. The key issue of this load-balancing algorithm has been addressed, namely the branch selection criterion. When this method is applied to a matrix multiplication algorithm running on a cluster of workstations, the optimal data distribution provides a significant performance increase of 44% over the equal distribution, which does not take into account communication overheads. Further, it is shown that, for a workstation cluster with random variations in their processing speeds, the execution time ratio of the equal and optimal distributions remains relatively unchanged. Thus the execution time of the optimal data distribution is no more sensitive to processor speed variation than the execution time of the equal distribution View full abstract»

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  • Note on optimal tile partition for space region of integrated-circuit geometry

    Publication Year: 1996 , Page(s): 246 - 248
    Cited by:  Patents (13)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    An OTP algorithm for solving the optimal tile-partitioning problem has recently been published by P.Y. Hsiao et al. (1993). The OTP algorithm makes use of an elimination algorithm to find a maximum set of nonintersecting critical partition edges. It is shown that this elimination algorithm is flawed View full abstract»

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  • Tabular techniques for generating Kronecker expansions

    Publication Year: 1996 , Page(s): 205 - 212
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    Tabular techniques and algorithms for generating Kronecker expansions are presented. The Kronecker expansions, a subclass of mixed-polarity Reed-Muller expansions, can be generated from Boolean functions Kronecker expansions of different polarity. The techniques can be used for completely and incompletely specified Boolean functions. The algorithms were implemented in Pascal and fully tested. Examples are given to illustrate the procedures View full abstract»

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  • Area efficient systolic interconnection networks

    Publication Year: 1996 , Page(s): 232 - 238
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (832 KB)  

    Area efficient VLSI design of interconnection networks is an important problem in multiprocessor design. In the context of ULSI technology, the delay in signal propagation along wires will become a significant limitation in designing large, fast networks. This limitation is particularly applicable for high wire organisations typically used in interconnection networks. In the paper, it is shown that classical cross-bar type interconnection networks, formed as systolic arrays, have better composite VLSI performance metrics than most popular interconnection networks that use high wire organisations even though systolic organisations have the disadvantage of being larger in terms of silicon area. The authors outline a new, hybrid architecture for interconnection networks that trades speed advantages of systolic arrays with area advantages of high wire organisations. An implementation, in VLSI, of a butterfly network using the proposed approach is described, and it is shown why this is useful in designing an area efficient interconnection network View full abstract»

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  • Performance-oriented synchronisation migration in a DOACROSS loop

    Publication Year: 1996 , Page(s): 224 - 231
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (760 KB)  

    A statement-level migration of synchronisation operation for performance enhancement is proposed. Theorems show that system performance is enhanced if the number of array elements in the maximal backward synchronisation region is reduced. This task is divided into three steps. First the redundant statements are moved out of the maximal backward synchronisation region by dependence analysis. Secondly, these two statements, which consist of a dependence source and its corresponding sink, respectively, are rewritten to reduce the range of the maximal backward synchronisation region. Finally, the redundant array elements are moved out of the maximal backward synchronisation region. Nine perfect benchmarks are employed to evaluate the performance enhancement after migration. Experimental results show that the enhancement is very significant View full abstract»

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  • Speculative parallel simulated annealing with acceptance prediction

    Publication Year: 1996 , Page(s): 219 - 223
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    In the paper, a novel problem-independent parallel realisation of the simulated annealing (SA) algorithm is proposed. By employing speculative computation, concurrency is introduced into the inherently sequential algorithm. This is achieved by predicting the acceptance of each generated move before the move is evaluated. Based on this prediction, subsequent moves can be proposed and evaluated before decisions on whether to accept or reject preceding moves are made. To preserve the sequential decision on whether to accept or reject subsequent to a prediction that is eventually wrong are discarded. A simple and prediction mechanism using previous move statistics is developed. Efficient realisation of the parallel SA algorithm on a ring multiprocessor architecture is described. Analytical and simulation performance results are presented. These results indicate that the authors' parallel SA is best implemented on a coarse to medium grain multiprocessor system. Factors affecting performance in actual implementations are also discussed View full abstract»

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  • Database of best T-codes

    Publication Year: 1996 , Page(s): 213 - 218
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    T-codes are variable-length codes that have been shown to provide excellent codeword synchronisation properties without any sacrifice in coding efficiency. Previously published results have used simulation techniques to ascertain the synchronising properties of each T-code. The author presents the first theoretical technique for calculating the synchronising delay of a T-code based on the code set's construction. The development of a database of best T-codes from which an optimally efficient code with superb synchronising properties can be easily chosen is also documented View full abstract»

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