Solid-State Circuits, IEEE Journal of
Issue 9 • Date Sep 1996
Society Sponsor
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Displaying Results 1 - 22 of 22
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An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)
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PDF (416 KB)
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An interpolating clock synthesizer
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PDF (856 KB)
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A CCD/CMOS focal-plane array edge detection processor implementing the multiscale veto algorithm
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PDF (872 KB)
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Design for velocity saturated, short-channel CMOS drivers with simultaneous switching noise and switching time considerations
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PDF (328 KB)
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A 3.3 V 625 kHz switched-current multiplier
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PDF (400 KB)
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A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme
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PDF (1144 KB)
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A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA
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PDF (552 KB)
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A rail-to-rail ping-pong op-amp
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PDF (380 KB)
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Aims & Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.
Meet Our Editors
Editor-in-Chief
Un-Ku Moon
Oregon State University, EECS
