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Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Issue 3 • Date Aug. 1996

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Displaying Results 1 - 25 of 30
  • Correction to "Efficient Transient Simulation of Lossy Packaging Interconnects Using Moment-Matching"

    Publication Year: 1996
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (34 KB)  

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  • Interconnect propagation delay modeling and validation for the 16-MB CMOS SRAM chip

    Publication Year: 1996 , Page(s): 605 - 614
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1004 KB)  

    In this paper, a closed-form expression for complementary metal-oxide semiconductor (CMOS) static random access memory component (SRAM) chip propagation delay is developed. This allows accurate calculation of the signal propagation delay of multilayer interconnects within the CMOS SRAM chip and also takes into account the delay of the CMOS SRAM cells driving the branched transmission line and the driving SRAM cell loading aspects of the interconnect line. Simulation results are presented to show the accuracy and efficiency of the propagation delay model. A case study of 16 MB CMOS SRAM chip performance evaluation is presented. The proposed closed-form delay expression results in an absolute maximum error smaller than 4.8% in comparison to the measured data. The proposed closed-form expression can be used for various high-speed, high-density multilayer interconnect SRAMs, dynamic random access memories (DRAMs), FPGAs, and application-specific integrated circuits (ASIC's) View full abstract»

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  • Design of a compact, high speed optical transceiver using two step overmolding

    Publication Year: 1996 , Page(s): 562 - 568
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB)  

    A low cost, compact optical transceiver has been designed for emerging fiber data distributed interface (FDDI) and fiber channel local-area networks (FCLANs). This transceiver has been designed to meet the growing volumes and rapidly falling prices in the FDDI marketplace. The package is designed to be fully compliant with an industry standard package outline and footprint. This optical data link (ODL) contains a duplex selection combining (SC) connector receptacle-compatible with the ANSI fiber channel and low-cost FDDI standards. With a single row of nine pins, the transceiver will occupy less than 1.0 in2 of board space. This ODL transceiver is designed using two-step overmold packaging technology. This technology integrates optical and electrical components in a single, sealed, transfer molded package. This package design uses a copper-based leadframe to provide low-cost interconnection and mass handling. The final assembly sequence was conceived using the latest design for simplicity (DFS) principles. This paper describes the design concept and challenges required to implement a full transceiver in such a small size. Thermal analysis results are discussed. Electrical design issues such as crosstalk and external noise immunity are also described. Initial performance results using preliminary design models will be reported View full abstract»

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  • Fatigue life estimation of surface mount solder joints

    Publication Year: 1996 , Page(s): 669 - 678
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1100 KB)  

    A novel and direct method to measure the stress-strain properties of surface mount solder joints is proposed in this paper. The specimen used in the experiments is a quad flat pack (QFP)-solder-printed circuit board (PCB) assembly and the fabrication of solder joints makes use of conventional surface mount technology (SMT). Mechanical cycling and thermal shock testing can be conducted directly on the specimen after assembly. In this manner, the specimen represents practical SMT solder joints in electronic products as far as possible. It is shown that the joint strain and stiffness of chip modules are good evaluation indices to reveal the fatigue status of solder joints. It is further proposed that the criterion of 50% load drop should be used for defining the fatigue life of solder joints. Finally, it is recommended that the total displacement Δδ2p be used to measure the strain-fatigue life relation for both leaded and leadless joints View full abstract»

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  • Full wave analysis of transmission lines in a multilayer substrate with heavy dielectric losses

    Publication Year: 1996 , Page(s): 621 - 627
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    The worldwide CMOS integrated circuits industry relies on heavily doped silicon wafers as the starting material for chip fabrication; the resulting integrated circuits are confined to the upper few microns of the wafer, which itself is as much as 600-μm thick. These heavily doped silicon substrates are not insulators, but are actually very lossy; a loss tangent of 105 at 1 MHz is a fairly typical characteristic of the wafers. Although it is becoming increasingly necessary to model accurately the currents which flow between transistors and interconnects into the substrates, existing computer-aided design (CAD) simulation packages fail to provide accurate results in modeling such heavy dielectric losses, because most CAD packages rely on small perturbation methods in the analysis of dielectric losses. In this paper, the problem of computing the electrical behavior of lossy dielectrics is analyzed by the full wave method, and the mutual capacitances of transmission lines above such heavily doped CMOS substrates are computed and compared with laboratory experimental measurements. Good agreement between analytical and measurement results has been obtained View full abstract»

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  • Design trade-offs for the last stage of an unregulated, long-channel CMOS off-chip driver with simultaneous switching noise and switching time considerations

    Publication Year: 1996 , Page(s): 481 - 486
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    Design trade-off relations for the last stage of a complementary metal-oxide-semiconductor (CMOS) off-chip driver that meets a prespecified normalized maximum simultaneous switching ground noise and a prespecified normalized time when the switched N-channel metal-oxide-semiconductor transistor (NMOST) leaves the saturation region are provided in this paper. To maintain system performance with control of 90-10% fall time and/or 10-90% rise time, the proposed trade-off relations are then modified numerically for design with prespecified fall/rise time. The proposed trade-offs relate the normalized simultaneous switching noise and the normalized switching time to driver size, load capacitance, ground/power path inductance, number of switching drivers, and input signal rise time. It will be shown that a dimensionless analysis method allows design to be extended to a variety of systems that share the same dimensionless performance. Such a feature will be demonstrated by SPICE simulations of circuits based upon the proposed design relations and MOS1 model, which agrees well with the design goals View full abstract»

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  • Thermal management of VCSEL-based optoelectronic modules

    Publication Year: 1996 , Page(s): 540 - 547
    Cited by:  Papers (7)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    Thermal management is critical to reliable optoelectronic modules based on vertical-cavity surface-emitting lasers (VCSELs). One critical thermal path to be managed is from a VCSEL to a case (heat sink), which is affected by packaging technologies and materials The measured VCSEL-to-case resistance of a laser with 8-μm aperture was 1650°C/W, and that of a 20-μm device was 1070°C/W. These thermal resistances are much larger than those for the edge-emitting lasers; advanced device and packaging technologies are being developed to reduce these resistances. To study the packaging effects, a three-dimensional (3-D) numerical model has been developed and calibrated by the measured data. The calibrated model was used to understand the difference in thermal behavior: 1) between a wire-bonded and a flip-chip VCSEL module, 2) between a single-VCSEL and an 8×8 VCSEL module, and 3) between a bottom-cooled and a top-cooled module View full abstract»

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  • Low temperature bonding of epitaxial lift off devices with AuSn

    Publication Year: 1996 , Page(s): 575 - 580
    Cited by:  Papers (4)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2052 KB)  

    The increasing demand for more advanced optoelectronic integrated circuits has created the need for bonding materials with different lattice constants (for example, GaAs on Si). In this paper, we report a new way for the bonding of epitaxial lift off (ELO) devices onto substrates. The multilayer structures investigated in this work produce a resulting AuSn alloy with approximately 84 wt.% gold, but can be bonded with a peak temperature of 235°C. The bonded samples were investigated with several standard surface analysis techniques like optical microscopy, scanning electron microscopy (SEM), and energy dispersive X-ray analysis (EDX) as well as mechanical tests. The results of our research allowed us to optimize the layer structure, the bonding parameters as well as the diffusion barriers View full abstract»

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  • Modeling, measurement, and simulation of simultaneous switching noise

    Publication Year: 1996 , Page(s): 461 - 472
    Cited by:  Papers (40)  |  Patents (49)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1136 KB)  

    The computer package designer depends on modeling power supply noises to ensure that system designs will function properly. Power supply noises can have a tremendous effect on system operation and performance. The circuit simulation of a system power distribution is very challenging since it requires accurate models of active devices, passive components, transmission lines, and a very large power distribution network. This paper presents the development of a high-frequency power distribution model for the simulation of simultaneous switching noise of a complementary metal-oxide-semiconductor (CMOS) chip on a multilayered ceramic substrate. Measurements are performed on a CMOS chip with simultaneously switching off-chip drivers (OCD's). The modeling approach is validated by the excellent agreement between the measurement waveforms and simulation results View full abstract»

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  • Measurements of the novel thermal conduction of a porphoritic heat sink paste

    Publication Year: 1996 , Page(s): 601 - 604
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    The thermal conduction of a solid/liquid porphoritic heat sink material having a specific geometry is reported. This new material consists of submicron-size diamond particles dispersed in n-decane at high packing fractions. Although each constituent has a measured decrease in thermal conduction with increasing temperature, the thermal conduction of the mixture shows a unique and significant increase with increasing temperature. This novel increase in thermal conduction has particular relevance to the thermal management of die that have uneven heat dissipation requirements. The material also has particular application in the construction and thermal design of multichip modules (MCM's) View full abstract»

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  • Level 1 crackfree plastic packaging technology

    Publication Year: 1996 , Page(s): 581 - 584
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    Cracking of plastic packages during printed circuit board (PCB) mounting is a serious customer concern as VLSI plastic packages house ever-increasing die sizes and are made thinner. Evolutionary improvements in package materials cannot prevent package cracking in the short term, especially in thin packages. A novel design, termed the “window flag”, employs a central hole punched in the die pad to minimize the metal-polymer interface and maximize the silicon-mold compound interface in the die pad region. This window flag design results in crackfree performance following Level 1 preconditioning in QFPs, TQFPs, and SOJs. This solution stems from the key discovery that the silicon-mold compound interface is intrinsically very strong under preconditioning stresses View full abstract»

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  • Time and frequency domain analysis of integral decoupling capacitors

    Publication Year: 1996 , Page(s): 518 - 522
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    Decoupling capacitors have been designed and included in high-speed packaging systems to avoid voltage drops across the power supply caused by interconnect inductance. They are also used to reduce simultaneous switching noise between the power supply and device I/O buffers. This paper will review three different measurement methods by which these capacitors were analyzed. It will discuss the possible detriments when making both low frequency and high frequency measurements on electronic packages and surface mount chip components using commercial instruments and fixtures. Two different types of high performance electronic packages with integral decoupling capacitors were analyzed. The models derived from the measurements were included in a circuit simulation to determine the effectiveness of decoupling noise between the device drivers and the system power supply. The results will provide insight into the effectiveness or these types of capacitors used within a high-speed electronic system View full abstract»

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  • Optical performance of low-cost self-aligned MCM-D based optical data links

    Publication Year: 1996 , Page(s): 554 - 561
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1120 KB)  

    We discuss the details of the design and performance of the optics proposed for a MCM-D based low-cost multimode optical data link. The optical system is completely self-aligned, taking advantage of flip-chip bonding, solder-bump self-alignment, mechanical self-alignment using silicon micromachining, and precision plastic components. Preliminary results demonstrate that the integral-lens design of the opto electronic device significantly effects the coupling efficiency and the requisite tolerances of the components that comprise the coupling optics. We show that coupling efficiencies of 70% or better are readily achievable with piece parts made using standard practices. These coupling efficiencies compare favorably with those in actively-aligned optical subassemblies used in current optical data link products View full abstract»

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  • Modeling and design of antennas for RF wireless systems

    Publication Year: 1996 , Page(s): 487 - 502
    Cited by:  Papers (1)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1080 KB)  

    Antennas are an important subcomponent for radio frequency (RF) wireless systems-oftentimes, performance improvements in the several dB range can be achieved by optimizing antenna design and position, which are very difficult to achieve with modifications to a radio. Antennas for RF wireless systems include portable RF remote antennas, for example for cellular phones, personal digital assistants (PDAs), handheld computers, and local-area network (LAN), wide-area network (WAN), and personal-area network (PAN) adapters for laptop computers, and base station antennas for these applications. Antennas for systems such as these have stringent cost, performance, and form factor specifications. This paper discusses the modeling and design of antennas for these applications, specifically a method of moments modeling tool which has been developed, special concerns in antenna design for portable RF remotes, and design of base station antennas View full abstract»

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  • A combined finite difference and analytic expression approach to crossover capacitance in a multilayer dielectric environment

    Publication Year: 1996 , Page(s): 615 - 620
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB)  

    The capacitances in the crossover regions of orthogonal transmission lines of finite thickness, fabricated on structures of the approximate dimensions of an integrated circuit, are evaluated in this paper by means of a combined finite difference and analytic expression method. The three-dimensional (3-D) finite difference method (FDM), using very fine mesh grids, is applied to an artificially defined region only a few microns in thickness, where orthogonal transmission lines on different metal layers of an integrated circuit cross one another. In the 600-μm thick dielectric region above the ground plane on the lower surface of an integrated circuit, analytic expressions of the solution to the Laplace equation are formulated. An artificial boundary is assumed to separate the substrate of the 600-μm thick integrated circuit from the thin active region on its uppermost surface where the active circuits and interconnects are actually fabricated, creating two separate regions which are treated using different approaches. An iterative procedure is employed to create a continuous interface between solutions across the boundary of the two regions generated by the two methods. The algorithm converges rapidly to very accurate solutions. The errors between this simulation method and laboratory measurements are within 8% for very small absolute values in the femtoFarad (fF) range. The field solutions are then converted into the equivalent circuit parameters. Finally, the waveshapes of propagating signal pulses are simulated by a networking program in a general electromagnetic modeling tool suite referred to as the Mayo Graphical Integrated Computer Aided Design Suite, or MagiCAD, in which the equivalent circuit model and capacitance values of the crossover problem are integrated View full abstract»

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  • Anisotropically conductive adhesive flip-chip bonding on rigid and flexible printed circuit substrates

    Publication Year: 1996 , Page(s): 644 - 660
    Cited by:  Papers (79)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4588 KB)  

    A systematic experiment on flip-chip bonding assembly using an anisotropically conductive adhesive (ACA) has been carried out. The assembled modules have been characterized by a number of environmental tests, including aging, constant humidity, temperature cycling, humidity cycling, shear, vibration, and shock testing. The results indicate that under optimum process conditions, high quality and high reliability joints can be achieved. Conduction failure mechanisms have been investigated using scanning electron microscopy (SEM) and transmission electron microscopy (TEM). The analysis shows that failure is dependent on competition between driving factors; thermal stress, elastic stress, expansion due to moisture absorption on one side, and the resistant factor, i.e., interatomic force. Variation of the filler size in the ACA, configurations of chips and boards, as well as bonding pressure and its distribution are among the most important factors that control the bonding quality and reliability View full abstract»

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  • Advanced COPNA-resin as a low temperature curing resin for high-density electronic packages

    Publication Year: 1996 , Page(s): 585 - 592
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    A novel type of low temperature curing resin for both LSI packages and high-density electronic packages was synthesized. The resin, named advanced COPNA-resin, was synthesized from naphthalene and 1,4-benzenedimethanol under an acid catalyst. The resin could be cured at lower temperature than generally used polyimide resin by more than 100°C. Beside the property of low temperature curing, the new resin exhibited attractive properties as an electronic insulating material of LSI packages and high-density packages: high glass transition temperature (250°C), low dielectric constant (εr3.1 for 1 MHz frequency), and small water absorption (0.37 wt.%). The resin could form thin films at the film thickness range from 5 to 20 μm when the spin speed range was from 1000 to 5000 rpm. The obtained thin films exhibited sufficient planarity in practical uses, and a precisely patterning property by a plasma etching method. In this paper, we also carried out the analysis for reaction process of the B-staged advanced COPNA-resin by using infrared absorption spectroscopy and 13C-NMR spectroscopy View full abstract»

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  • A surface mount single-mode laser module using passive alignment

    Publication Year: 1996 , Page(s): 524 - 531
    Cited by:  Papers (14)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1696 KB)  

    A novel single-mode laser module has been developed using a surface mounting technique. A simple receptacle structure for the module output port is also designed. This module offers high coupling efficiency and optical coupling using the passive alignment technique. A module size of 7.6 mm×12 mm×3 mm is achieved, which is very friendly for the automatic assembly line as well as the module mounting process on circuit boards. A laser diode (LD) is passively positioned by utilizing a pair of alignment marks, each of which located on the LD and Si substrate, a single-mode fiber with a microhemispherical lens on the fiber facet is self-aligned on a Si-V groove. The LD to single-mode fiber coupling loss and standard deviation are found to be 5 dB and 1.5 db, respectively. The simple receptacle structure enables one to use this module in the same way as conventional surface mount electrical components. The module assembly process is simplified by successively mounting subassembly parts View full abstract»

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  • Numerical stress analysis of resin cracking in LSI plastic packages under temperature cyclic loading

    Publication Year: 1996 , Page(s): 593 - 600
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB)  

    Numerical stress analysis of resin cracking occurring in plastic packages during temperature cyclic loading was carried out using a thermoelastic finite-element method (FEM) for the nonlinear contact problem. Through the use of the linear fracture mechanics approach to the bimaterial problem, the analysis provides a fracture parameter and indicates the direction in which resin cracking occurs. Temperature cycling tests using actual plastic packages were also performed to verify the validity of the analysis results experimentally. It was found that the test results agreed well with the analytical results. It was also clear that the delamination occurring between dissimilar materials determines the degree to which resin cracking occurs quantitatively and the most harmful delamination occurs in the die bonding layer. The resin cracking mechanism was studied and a countermeasure against it was proposed View full abstract»

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  • Characterization of a small peripheral array package

    Publication Year: 1996 , Page(s): 512 - 517
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    This paper provides details on a very small peripheral array (VSPA) cavity package with high I/O's that is surface mountable on a printed circuit board (PCB). The package consists of 320 leads and measures 27 mm on a side. This paper discusses the package attributes, comparison to equivalent packages, and characterization of the package parasitics up to 3.5 GHz View full abstract»

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  • 622 Mb/s/channel parallel digital optical receiver array module using hybrid packaging

    Publication Year: 1996 , Page(s): 548 - 553
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (860 KB)  

    Given the high data rates (>500 Mb/s) achievable in optical links using current device technologies, low cost packaging of transmitters and receivers plays a key role in rendering them viable for short-haul data communication networks. The authors report a 12 channel, fully digital, hybrid receiver module for a synchronous parallel optical datalink operating at 622 Mb/s/channel. The use of a multichip module (MCM) and the passive alignment of the MT-connectorized multimode ribbon fiber to the photodetector array resulted in a simple low cost packaging solution View full abstract»

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  • Laser-diode array packaging in opto-electronic multichip modules

    Publication Year: 1996 , Page(s): 628 - 634
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB)  

    An opto electronic multichip module (OE-MCM) constructed from optical polyimide waveguides on an OE substrate has been developed for high-speed, wideband communication systems. This paper describes the packaging of the laser-diode (LD) array on the OE substrate, which is composed of low-loss (0.4 dB/cm at 1.3 μm) optical polyimide waveguides on a copper-polyimide multilayer substrate. High-speed (Gbit/s) electrical signals are transmitted through electrical lines in the copper-polyimide layers. A junction-up, five-channel InGaAsP edge-emitting LD array is aligned to the waveguides in the plane direction with an error margin of 2 μm by using a standard surface for vertical positioning. The bottom of the LD array is connected to columnar thermal vias under the bonding area for heat dissipation. The emitted light power is considered to be stable because no kinks and good linearity are observed in the I-L characteristics of the coupled LD array. The coupling loss was estimated to be 6.5 dB with a deviation between channels of ±0.3 dB View full abstract»

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  • High Q-factor inductors integrated on MCM Si substrates

    Publication Year: 1996 , Page(s): 635 - 643
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (992 KB)  

    High quality factor (Q) inductors were designed and fabricated on high-resistivity (2000 Ω·cm) Si substrates with multichip module (MCM) fabrication technology. A Q-factor of 30 was achieved for an inductor of 4 nH at 1-2 GHz. To enhance the Q-factor and reduce the parasitic coupling capacitance, a staggered double metal-layered structure was utilized by taking advantage of the double-layered metal lines in MCM. With electromagnetic simulation tools, computer-aided analysis was used to optimize the device characteristics. The skin effect and the lossy substrate effect on the performance of the radio frequency (RF) thin-film inductors were studied. The fabrication process used polyimide as the dielectric layer and aluminum as the metal layer. The use of the low dielectric-constant material, polyimide, reduces the parasitic coupling capacitance between metal lines and increases the quality factor and the self-resonant frequency for the RF integrated inductors View full abstract»

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  • Reliability studies of surface mount solder joints - effect of Cu-Sn intermetallic compounds

    Publication Year: 1996 , Page(s): 661 - 668
    Cited by:  Papers (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1768 KB)  

    Cu-Sn intermetallic compounds (IMCs), formed at the interface between the solder and the copper substrate are found to play a dominant role in determining the thermal fatigue life of surface mount solder joints fabricated from a conventional infrared reflow process. In order to predict the growth of this IMC layer during the operating life of the solder joint and its effect on the thermal fatigue life, the formation characteristics of the IMC's in 0805 and 1206 LCCC solder joints are systematically studied in this investigation. Only the stable Cu6 Sn5% η-phase intermetallic compound was observed in all as-solidified solder joints as confirmed by scanning electron microscopy (SEM) and energy dispersive X-ray (EDX). The mean layer thickness was found to increase almost linearly with reflow time up to about 200 s. The thickness of the interfacial IMC layer increased with increasing reflow temperature for 0805-type solder joints up to around 250°C and reached a saturated thickness of 2.5 μm beyond this temperature. Additional intermetallic formation due to higher reflow temperature or longer reflow time would appear as Cu-Sn whiskers in the bulk solder of the joint. The copper land pad size and quality of component lead metallization were also found to greatly affect the formation of Cu-Sn IMC in surface mount solder joints, and hence its reliability in terms of thermal fatigue life and mechanical properties View full abstract»

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  • Multireflection algorithm for timed statistical coupled noise checking

    Publication Year: 1996 , Page(s): 503 - 511
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (804 KB)  

    An algorithm that completely characterizes the coupled noise for a pairwise coupled network with arbitrary lengths and reflection coefficients has been implemented in a coupled noise checking software. In this paper, an overview of the coupled noise methodology is briefly described so that the development of the reflection algorithm can be easily understood. Comparisons of the coupled noise predictor results to the ones obtained from detailed circuit simulation are presented. These results quantify the coupled noise predictor accuracy improvement when the timed noise reflections are included in the total coupled noise calculations and they demonstrate the computational time advantage that this approach has over device level simulations View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope