By Topic

Solid-State Circuits, IEEE Journal of

Issue 8 • Date Aug. 1996

Filter Results

Displaying Results 1 - 21 of 21
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • A -80 dB THD, 4 Vpp switched capacitor filter for 1.5 V battery-operated systems

    Page(s): 1214 - 1219
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    A fully differential fifth-order SC filter that can operate from power supplies as low as 1.5 V featuring a -80 dB THD up to 4 Vpp output voltage is presented. A measured p-weighted noise of 120 μVrms leads to a dynamic range of 81.5 dB. This circuit is used as reconstruction filter for a low voltage 14-b DAC. The very low voltage operation has been possible by integrating a regulated voltage-multiplier on the same chip. The filter active area is 0.54 mm 2 in a 0.8 μm CMOS technology. Typical power consumption is 0.8 mW at 1.5 V supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter

    Page(s): 1201 - 1207
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    This paper describes the design of a CMOS capacitor-ratio-independent and gain-insensitive algorithmic analog-to-digital (A/D) converter. Using the fully differential switched-capacitor technique, the A/D converter is insensitive to capacitor-ratio accuracy as well as finite gain and offset voltage of operational amplifiers. The switch-induced error voltage becomes the only major error source, which is further suppressed by the fully differential structure. The proposed A/D converter is designed and fabricated by 0.8 μm double-poly double-metal CMOS technology. The op-amp gain is only 60 dB and no special layout care is done for capacitor matching. Experimental results have shown that 14-b resolution at the sampling frequency of 10 kHz can be achieved in the fabricated A/D converter. Thus it can be used in the applications which require low-cost high-resolution A/D conversion View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3.3-V BiCMOS current-mode logic circuits for high-speed adders

    Page(s): 1165 - 1169
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    New high-speed BiCMOS current mode logic (BCML) circuits for fast carry propagation and generation are described. These circuits are suitable for reduced supply voltage of 3.3-V. A 32-b BiCMOS carry select adder (CSA) is designed using 0.5-μm BiCMOS technology. The BCML circuits are used for the correct carry path for high-speed operation while the rest of the adder is implemented in CMOS to achieve high density and low power dissipation. Simulation results show that the BiCMOS CSA outperforms emitter coupled logic (ECL) and CMOS adders View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Delay propagation effect in transistor gates

    Page(s): 1184 - 1189
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    Wide VLSI transistors suffer additional switching delays due to signal propagation when passing through the resistive gate polysilicide. We model and evaluate this resistive effect and define an analytical expression in terms of extra propagation term. This delay can be reduced by breaking up a single wide transistor into smaller transistors connected and driven in parallel. This work develops expressions for deciding how many parallel transistors should be employed so as to limit the additional delay caused by the resistive polysilicide to within desired bounds. The expressions are validated by comparing calculated delay results with those from HSPICE simulations View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noise in distributed MESFET preamplifiers

    Page(s): 1100 - 1111
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    The theory of noise in a distributed MESFET preamplifier is developed. From this, it is shown that the equivalent input noise current density of a distributed preamplifier of an optical receiver can be improved by using large gate line matching impedance and appropriate scaling of the MESFET width. A front-end tuning circuit was designed using filter theory to further improve the noise performance of the preamplifier. A monolithic GaAs MESFET distributed preamplifier was fabricated with on chip front-end tuning components. Using a 35 μm InGaAs p-i-n photodiode, the preamplifier was shown to have an equivalent input noise current density of 8 pA/√Hz and an 8 GHz bandwidth. To date, this is the best known result for a 0.8 μm GaAs MESFET process View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Leading-zero anticipatory logic for high-speed floating point addition

    Page(s): 1157 - 1164
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB)  

    This paper describes a new leading-zero anticipatory (LZA) logic for high-speed floating-point addition (FADD). This logic carries out the pre-decoding for normalization concurrently with addition for the significand. It also performs the shift operation of normalization in parallel with the rounding operation. The use of simple Boolean algebra allows the proposed logic to be constructed from a simple CMOS circuit. Its area penalty is as small as 30% of the conventional LZA method. The FADD core using the proposed logic was fabricated by 0.5 μm CMOS technology with triple metal interconnections and runs at 164 MHz under the condition of VDD=3.3 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 200 MHz CMOS Q-enhanced LC bandpass filter

    Page(s): 1112 - 1122
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1120 KB)  

    This paper presents design techniques and performance bounds for implementing Q-enhanced, LC bandpass filters in silicon IC technologies. These filters offer significant advantages over switched capacitor and Gm-C based designs, including higher frequency of operation and lower power consumption for a given dynamic range. A prototype 200 MHz, fourth-order filter implemented in a 2 μm n-well CMOS process is described, and measured performance is compared with theoretical predictions. The prototype filter operates at a selectivity Q of 100 and draws less than 8 mA when operating from 3 to 5 V supplies, making it potentially suitable for use as a first IF filter in modern cellular and PCS receivers View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A BiCMOS limiting amplifier for SONET OC-3

    Page(s): 1197 - 1200
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB)  

    This paper presents a Synchronous Optical NETwork (SONET) OC-3 155.52 Mb/s limiting amplifier, which is implemented in a 1.0 μm double-poly double-metal N-well BiCMOS technology. Composed of amplifier cells, a slicer, an output driver, and offset cancellation circuits, this limiting amplifier allows an input dynamic range of 36 dB (6 mVpp~400 mVpp) and provides a constant output 1 V pp across a 50 Ω load for long-haul 40 km application. The active area of this limiting amplifier is 0.8 mm×3.0 mm. It consumes 130 mW from a single -5 V supply voltage View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A comparative study on the various monolithic low noise amplifier circuit topologies for RF and microwave applications

    Page(s): 1220 - 1225
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    This paper critically compares the various monolithic low noise amplifier (LNA) circuit topologies using BiCMOS or MESFET technologies for RF and microwave applications, in addition to the conventional techniques, five newly proposed schemes for the simultaneous noise and input power matching are extensively compared with each other at microwave frequencies. At L-band, the best scheme is found to be the proposed cascode inductive series feedback (CCSF) or common-source inductive series feedback (CSSL)+common-gate inductive parallel feedback (CGPF) when 0.5 μm GaAs MESFET is used, while it is cascode resistive parallel feedback (CCPF) when n-p-n BJT is used. At C- and X-bands, the proposed CGPF exhibits the best performance. Other than CGPF, the CSSL+CGPF seems to he the best at 6 GHz, and both CCPF+CGPF and CSSL+CGPF are recommended at 12 GHz. Finally, to verify the feasibility of this approach, a CCPF has been fabricated with 0.5 μm GaAs MMIC technology, of which measured results agree well with the simulated ones View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces

    Page(s): 1170 - 1176
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm2 for the digital PLL and 0.44 mm2 for the analog PLL. It can handle an input data rate up to 280 Mb/s View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A wide dynamic range continuously adjustable CMOS current mirror

    Page(s): 1208 - 1213
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    A novel circuit realization of a CMOS current mirror with wide input dynamic range and continuously adjustable gain is presented. The proposed current mirror is linear with respect to signal current in the strong inversion as well as in the subthreshold region of MOSFET operation. The gain is controlled by the same control signal in both regions. The circuit is analyzed using a numerical unified MOSFET model which covers both operating regions. The implemented current mirror is adjustable over more than eight decades of signal current View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • GaAs Schmitt trigger memory cell design

    Page(s): 1190 - 1192
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    A novel GaAs five-transistor static memory cell derived from a Schmitt trigger is proposed. The memory cell overcomes MESFET subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small area and as well as fast read/write cycles. A 1 Kb prototype implemented in 1 μm nonself-aligned GaAs MESFET technology exhibited read and write access times of the order of 2.0 ns View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s

    Page(s): 1076 - 1090
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1632 KB)  

    In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the IC's must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gates

    Page(s): 1177 - 1183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (804 KB)  

    A novel high-speed circuit implementation of the (31,5)-parallel counter (i.e., population counter) based on capacitive threshold logic (CTL) is presented. The circuit consists of 20 threshold logic gates arranged in two stages, i.e., the parallel counter described here has an effective logic depth of two. The charge-based CTL gates are essentially dynamic circuits which require a periodic refresh or precharge cycle, but unlike conventional dynamic CMOS gates, the circuit can be operated in synchronous as well as in asynchronous mode. The counter circuit is implemented using conventional 1.2 μm double-poly CMOS technology, and it occupies a silicon area of about 0.08 mm2. Extensive post-layout simulations indicate that the circuit has a typical input-to-output propagation delay of less than 3 ns, and the test circuit is shown to operate reliably when consecutive 31-b input vectors are applied at a rate of up to 16 Mvectors/s. With its demonstrated data processing capability of about 500 Mb/s, the CTL-based (31,5) parallel counter offers a number of application possibilities, e.g., in high-speed parallel multiplier arrays and data encoding circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • GaAs dynamic memory design

    Page(s): 1193 - 1196
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    Subthreshold leakage loss is a serious problem for GaAs dynamic memory. Since the leakage current in a MESFET is several orders of magnitude higher than that in a MOSFET, it is difficult to retain the charge at dynamic nodes resulting in data storage errors, In order to solve this problem, a novel DRAM architecture is proposed. The design is based on a cell consisting of a MESFET switch and a metal-insulator-metal (MIM) planar capacitor as the storage element. The leakage current is reduced by a level-shift technique and a self-biased transistor is used to maintain the dynamic charge during the sense period. A high performance sense amplifier is used to detect small bit line voltage changes and refresh the stored data. A 1 Kb prototype, fabricated in a 1 μm nonself-aligned GaAs MESFET technology, exhibited a total read/write access time of the order of 3 ns View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A capacitive threshold-logic gate

    Page(s): 1141 - 1150
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1124 KB)  

    A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compact multiple-valued multiplexers using negative differential resistance devices

    Page(s): 1151 - 1156
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    Quantum electronic devices with negative differential resistance (NDR) characteristics have been used to design compact multiplexers. These multiplexers may be used either as analog multiplexers where the signal on a single select line selects one out of four analog inputs, or as four-valued logic multiplexers where the select line and the input lines represent one of four quantized signal values and the output line corresponds to the selected input. Any four-valued logic function can be implemented using only four-valued multiplexers (also known as T-gates), and this T-gate uses just 13 devices (transistors) as compared to 44 devices in CMOS. The design of the T-gate was done using a combination of resonant tunneling diodes (RTD's) and heterojunction bipolar transistors (HBT's) with the folded I-V characteristic (NDR characteristic) of the RTD's providing the compact logic implementation and the HBT's providing the gain and isolation. The application of the same design principles to the design of T-gates using other NDR devices such as resonant tunneling hot electron transistors (RHET's) and resonant tunneling bipolar transistors (RTBT's) is also demonstrated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Over-30-GHz limiting amplifier ICs with small phase deviation for optical communication systems

    Page(s): 1091 - 1099
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (992 KB)  

    For a high-speed limiting amplifier with small phase deviation, a new design technique using a uniplanar passive balun and a narrow-band matching network is proposed. It is revealed that a device with small bias-dependence of parasitic capacitances, such as a high electron mobility transistor (HEMT), and a differential operation using passive baluns enables phase deviations at very high frequency to be reduced. Furthermore, suppressing harmonics can reduce phase deviation in a limiting amplifier, which operates in the highly nonlinear region. To verify these design techniques, two types of limiting amplifier ICs using an InP HEMT and AlGaAs/GaAs BCT technology were designed and fabricated. These IC's feature narrow-band matching circuits for input and output using transmission lines and uniplanar CPW-slot transition baluns for differential signals. The devices achieved high frequency operation of over 30 GHz with small phase deviations View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power-efficient metastability error reduction in CMOS flash A/D converters

    Page(s): 1132 - 1140
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (964 KB)  

    A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2 n-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-μm CMOS with measured metastability error rates of less than 10 -12 errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10-4 errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2n-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel multi-input floating-gate MOS four-quadrant analog multiplier

    Page(s): 1123 - 1131
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1060 KB)  

    A novel four-quadrant analog multiplier using multi-input floating-gate MOS (MFMOS) transistors has been designed and fabricated using a 2-μm double-poly double-metal P-well CMOS process. It is essentially based on the quarter-square technique which relies on the square-law characteristic of the MOS transistor in the saturation region. The multiplier is realized with only four MFMOS transistors and a current source. The input range is 100% of the supply voltage and accepts either differential, single-ended, or floating input signals. Measured nonlinearity and total harmonic distortion are 0.2% and 0.5%, respectively, under full scale input conditions. Input noise is 170 μV (rms), giving a 95 dB input dynamic range. The power dissipation is 1.1 mW and bandwidth is 12 MHz. Second-order effects on the multiplier performance have also been analyzed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan