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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 8 • Date Aug 1996

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Displaying Results 1 - 17 of 17
  • Analysis and synthesis of concurrent digital circuits using control-flow expressions

    Publication Year: 1996 , Page(s): 854 - 876
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2248 KB)  

    In this paper, we present a novel modeling style and control synthesis technique for system-level specifications that are better described as a set of concurrent descriptions, their synchronizations, and constraints. The proposed synthesis procedure considers the degrees of freedom introduced by the concurrent models and by the environment in order to satisfy the design constraints. Synthesis is divided into two phases. In the first phase, the original specification is translated into an algebraic system, for which complex control-flow constraints and quantifiers of the design are introduced. In the second phase, we translate the algebraic formulation into a finite-state representation, and we derive an optimal control-unit implementation for each individual concurrent part. In the implementation of the controllers from the finite-state representation, we use flexible objective functions, which allow designers to better control the goals of the synthesis tool, and thus incorporate as much as possible their knowledge about the environment and the design View full abstract»

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  • Classification and identification of nonrobust untestable path delay faults

    Publication Year: 1996 , Page(s): 845 - 853
    Cited by:  Papers (70)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB)  

    Recently published results have shown that, for many circuits, only a small percentage of path delay faults is robust testable, Among the robust untestable faults, a significant percentage is not nonrobust testable either. In this paper, we take a closer look at the properties of these nonrobust untestable faults with the goal of determining whether and how these faults should be tested. We define a path delay fault to be functional redundant (f-redundant) if, regardless of the delays at all other signals, the circuit performance will not be determined by the path. These paths are false paths-regardless of the delays of all signals. Therefore, these paths cannot and need not be tested. We present a sufficient condition for functional redundancy. We will show that nonrobust untestable faults are not necessarily f-redundant. For those nonrobust untestable but functional irredundant (f-irredundant) faults, the corresponding path may become a true path, and thus may determine the circuit performance under the faulty condition. We present an efficient algorithm for identifying f-redundant path delay faults. Results show that a significant percentage of path delay faults are f-redundant for ISCAS'85 benchmark circuits. Identification of f-redundant faults has two important applications: 1) it provides a more realistic fault coverage measure (as the number of detected faults divided by the total number of f-irredundant faults), 2) For circuits with a large number of paths, testing only a subset of paths becomes a common practice. The path selection process can be guided to avoid selecting f-redundant paths. To illustrate this application, we present an algorithm for selecting a set of f-irredundant path delay faults that includes at least one of the longest f-irredundant paths for each signal in the circuits View full abstract»

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  • Performance optimization using template mapping for datapath-intensive high-level synthesis

    Publication Year: 1996 , Page(s): 877 - 888
    Cited by:  Papers (35)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1116 KB)  

    This paper introduces a new approach to performance-driven template mapping for high-level synthesis. Template mapping, the process of mapping high-level algorithmic descriptions to specialized hardware libraries or instruction sets, involves template matching, template selection, and clock selection. Efficient algorithms for each are presented, and novel issues such as partial matching are addressed. The paper focuses on datapath-intensive ASIC design, though the concepts are also highly applicable to compiler development. Experimental results on examples from real applications show significant improvements in throughput with limited area overhead View full abstract»

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  • Automatic layout recycling based on layout description and linear programming

    Publication Year: 1996 , Page(s): 959 - 967
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1152 KB)  

    When a fabrication process is renewed, of practical importance is how to make the best use of layout resources so far accumulated for old fabrication processes. The present paper describes an automatic recycling system for layout data once used dedicatedly for functional cells of the standard-cell level. The main process of this system is i) to transform given layout data into a layout description format expressed in parameters associated with shapes, sizes, and locations of layout elements, and then ii) to resynthesize an optimal layout in accordance with a new set of design rules by means of a graph theoretic linear programming approach. A part of implementation results is also shown View full abstract»

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  • Comparison of temperature models for the drain current of MESFET's

    Publication Year: 1996 , Page(s): 968 - 976
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    In this paper, the Curtice, Shoucair, Selmi, and Rodriguez nonlinear dc drain current thermal models for the GaAs MESFET device are compared to determine which best fulfills the nonlinear criteria. The comparison is performed using a variety of MESFET's of varying gate-widths, pinch-off voltages, and number of fingers to assess the consistency of the models. The nonlinear criteria are assessed with the models applied under different bias and temperature conditions. The execution speed of the models is also assessed, since this is a significant feature from a circuit simulation point of view View full abstract»

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  • An improved linear placement algorithm using node compaction

    Publication Year: 1996 , Page(s): 952 - 958
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    Linear placement has several applications in the design of very large scale integrated (VLSI) circuits. Several authors have recently shown that node clustering or compaction enhances the performance of iterative algorithms. This paper describes a technique to extract clusters by means of an algorithm that identifies a maximum weight matching in a path graph in linear time. The resulting linear placement algorithm (CLP) combines node compactions and iterative improvement in an efficient and effective approach. The benefit of compaction is quite visible. Comparisons of the results of CLP with and without compaction on several test cases show the dramatic effect of compaction on the final solution. The approach of CLP is an efficient improvement of the linear placement algorithm of Saab and Chen [1994]. On many instances with known optimal solutions, CLP also achieves an optimal solution. The dependency of the results of CLP on the initial placement is minimal, since solutions found by CLP using many different starts do not significantly differ from each other. Under suitable assumption, CLP can be shown to run in O(nP), where n and P are the number of nodes and the number of pins of the input circuit, respectively View full abstract»

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  • A neural network model for multilayer topological via minimization in a switchbox

    Publication Year: 1996 , Page(s): 1012 - 1020
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    This paper presents a new approach using a neural network model for the multilayer topological via minimization problem in a switchbox. Our algorithm consists of three steps: 1) dividing multiterminal nets into two-terminal nets, 2) finding a layer-assignment of the two-terminal nets by a neural network model so as to minimize the number of unassigned nets, and 3) embedding one via for each unassigned net by Marek-Sadowska's algorithm. The neural network model is composed of N×M processing elements to assign N two-terminal nets in an M-layer switchbox. The performance of our algorithm is verified by 15 benchmark problems where it can find optimum or near-optimum solutions. In the two-layer Burstein's switchbox, our algorithm finds a 15-via solution while the best known solution requires 20 vias View full abstract»

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  • GALLO: a genetic algorithm for floorplan area optimization

    Publication Year: 1996 , Page(s): 943 - 951
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    The paper describes a Genetic Algorithm for the Floorplan Area Optimization problem. The algorithm is based on suitable techniques for solution encoding and evaluation function definition, effective cross-over and mutation operators, and heuristic operators which further improve the method's effectiveness. An adaptive approach automatically provides the optimal values for the activation probabilities of the operators. Experimental results show that the proposed method is competitive with the most effective ones as far as the CPU time requirements and the result accuracy is considered, but it also presents some advantages. It requires a limited amount of memory, it is not sensible to special structures which are critical for other methods, and has a complexity which grows linearly with the number of implementations. Finally, we demonstrate that the method is able to handle floorplans much larger (in terms of number of basic rectangles) than any benchmark previously considered in the literature View full abstract»

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  • OBDD-based function decomposition: algorithms and implementation

    Publication Year: 1996 , Page(s): 977 - 990
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1124 KB)  

    This paper presents algorithms for disjunctive and nondisjunctive decomposition of Boolean functions and Boolean methods for identifying common subfunctions from multiple Boolean functions. Ordered binary decision diagrams are used to represent and manipulate Boolean functions so that the proposed methods can be implemented concisely. These techniques are applied to the synthesis of look-up table based field programmable gate arrays and results are presented View full abstract»

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  • Solving the net matching problem in high-performance chip design

    Publication Year: 1996 , Page(s): 902 - 911
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (900 KB)  

    In high-performance chip design, the problem of net matching is often critical for achieving correct circuit performance. We adopt a conservative design, to route all matched nets with identical topologies and equal wire lengths to achieve zero skew. The problem is formulated as a variant of the D-dimensional Steiner tree problem. We propose a two-stage solution. The first stage uses an iterative improvement strategy to generate the Steiner tree topology for all the nets. The second stage places the nodes using one of two methods. The first approach expresses the optimal Steiner node positions as a linear programming solution, with average computational complexity O(n2 m2), where n is the number of nets and m is the number of pins. Improved efficiency is achieved under the other approach by transforming the Manhattan metric to an l norm using a 45° rotation of the solution space. The norm is then approximated by either an lλ norm, for suitably large values of λ, or an exponential “penalty” function. The solution space in both approaches becomes strictly convex, allowing us to apply a greedy approach which converges to an optimal solution with great efficiency, leading to a dramatic speed-up versus the linear programming approach View full abstract»

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  • Fast and simple method for calculating the minority-carrier current in arbitrarily doped semiconductors

    Publication Year: 1996 , Page(s): 1025 - 1026
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    A fast numerical method for evaluating the minority-carrier current injected into arbitrarily doped semiconductor regions is presented. The method is based on an efficient regional approach and is very easy to implement View full abstract»

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  • Wire sizing as a convex optimization problem: exploring the area-delay tradeoff

    Publication Year: 1996 , Page(s): 1001 - 1011
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (980 KB)  

    An efficient solution to the wire sizing problem using the Elmore delay model is proposed. Two formulations of the problem are put forth. In the first, the minimum interconnect delay is sought, while in the latter, we minimize the net delay under delay constraints at the leaf nodes; previous approaches solve only the former problem. Theoretical results on these problems are proved, and two algorithms are presented. One is a sensitivity-based heuristic, while the other is a rigorous convex optimization problem. It is shown experimentally that the sensitivity-based heuristic gives near-optimal results with reasonable runtimes. A smooth area-delay tradeoff is shown, and results are presented to illustrate the fact that sizing for minimum delay is not a good engineering goal. Instead, a delay goal of even 15% over the minimum provides significantly better engineering solutions View full abstract»

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  • A weighted random pattern test generation system

    Publication Year: 1996 , Page(s): 1020 - 1025
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    This paper describes a weight generation algorithm that is driven by tests created by a test generator. New concepts with regard to throwing away ineffective weight sets are developed as an integral part of the system. Various parameters that help improve the effectiveness of the weight generation system are discussed View full abstract»

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  • An approach for multilevel logic optimization targeting low power

    Publication Year: 1996 , Page(s): 889 - 901
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1368 KB)  

    This paper shows that using don't cares computed for area optimization during local node minimization may result in an increase in the power consumption of other nodes in a Boolean network. It then presents techniques for computing a subset of observability and satisfiability don't care conditions that can be used freely to optimize the local function of nodes. The concept of minimal variable support is then used to optimize the local function of each node for minimum power using its power relevant don't care set, that is, to reimplement the local function using a modified support that has a lower switching activity. Empirical results on a set of benchmark circuits are presented and discussed View full abstract»

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  • GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits

    Publication Year: 1996 , Page(s): 991 - 1000
    Cited by:  Papers (46)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB)  

    This paper deals with automated test pattern generation for large synchronous sequential circuits and describes an approach based on genetic algorithms. A prototype system named GATTO is used to assess the effectiveness of the approach in terms of result quality and CPU time requirements. An account is also given of a distributed version of the same algorithm, named GATTO*. Being based on the PVM library, it runs on any network of workstations and is able to either reduce the required time, or improve the result quality with respect to the monoprocessor version. In the latter case, in terms of Fault Coverage, the results are the best ones reported in the literature for most of the largest standard benchmark circuits. The flexibility of GATTO enables users to easily tradeoff fault coverage and CPU time to suit their needs View full abstract»

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  • A wire length estimation technique utilizing neighborhood density equations

    Publication Year: 1996 , Page(s): 912 - 922
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB)  

    This paper presents a new wire length estimation technique for row-based design. Noting that the local topological structure of the network is often reflected in the local structure of the placement, we present a technique of topological analysis of the network, in which the local structure of the network is characterized by a growing sequence of multilevel neighborhoods. By assuming a pointwise independent branching process, we derive equations for the probability density of multilevel neighborhoods. The wire length distribution is found by solving these equations. For thirteen industrial circuits tested, this technique gives an average of 15.1% estimation accuracy View full abstract»

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  • Automation of IC layout with analog constraints

    Publication Year: 1996 , Page(s): 923 - 942
    Cited by:  Papers (63)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2516 KB)  

    A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu