By Topic

Solid-State Circuits, IEEE Journal of

Issue 7 • Date Jul 1996

Filter Results

Displaying Results 1 - 25 of 26
  • Automated design of switched-current filters

    Page(s): 898 - 907
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (988 KB)  

    This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S2I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 μm standard CMOS process, they demonstrate state-of-the-art performance View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-voltage, low-power CMOS delay element

    Page(s): 966 - 971
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    A low-voltage, low-power CMOS delay element is proposed. With a unit CMOS inverter load, a delay from 2.6 ns to 76.3 ms is achieved in 0.8 μm CMOS technology. Based on a CMOS thyristor concept, the delay value of the proposed element can be varied over a wide range by a control current. The inherent advantage of a CMOS thyristor in low voltage domains enables this delay element to work down to the supply voltage of 1 V while the threshold voltage of the nMOS and pMOS transistors are 840 mV and -770 mV, respectively. The designed delay value is less sensitive to supply voltage and temperature variation than RC-based or CMOS inverter-based delay elements. Temperature compensation and jitter performance in a noisy environment are also discussed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design considerations for CMOS digital circuits with improved hot-carrier reliability

    Page(s): 1014 - 1024
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (τ) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS

    Page(s): 890 - 897
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (892 KB)  

    A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

    Page(s): 972 - 980
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (956 KB)  

    Novel 2.5 V CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 200 MHz superscalar RISC processor. The NTP circuit has two advantages: high noise immunity and high speed. Floating point operations can be executed in a two cycle latency using the high speed NTP circuit. The leakless buffer circuit with NMOS transmission gate in 128 floating point registers makes possible both high integration and low power dissipation, since the circuit causes no leak current without precharging the number of read lines. The processor makes use of 0.3 μm CMOS technology with a 2.5 V power supply and four metal layers. The floating point macrocell has 380 thousand transistors and dissipates 350 mW at 200 MHz. The peak performance of the floating point macrocell is 400 MFLOPS View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Differential current switch logic: a low power DCVS logic family

    Page(s): 981 - 991
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1056 KB)  

    Differential current switch logic (DCSL), a new logic family for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL circuits are capable of implementing high complexity high fan-in gates without compromising gate delay. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit. Three forms of DCSL circuits have been developed with varying benefits in speed and power. SPICE simulations of circuits designed using the 1.2 μm MOSIS SCMOS process indicate a factor of two improvement in speed and power over comparable DCVS gates for moderate tree heights View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Offset-trimming bit-line sensing scheme for gigabit-scale DRAM's

    Page(s): 1025 - 1028
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    A new offset-trimming bit-line sensing scheme is described which is suitable for gigabit-scale DRAM's. This sensing scheme can suppress the sensitivity degradation caused by the large electrical parameter variation of deep submicron transistors. The effective offset voltage dependence on trimming time is analyzed and verified with simulation results. As compared with a conventional direct sensing scheme, the proposed scheme shows remarkable improvement on the sensitivity. A test device was fabricated with a 0.25 μm CMOS technology and its measurement results indicate the successful operation of offset-trimming View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A multiplier-accumulator macro for a 45 MIPS embedded RISC processor

    Page(s): 1067 - 1071
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point of architecture is to utilize a full adder array and the Booth's encoder twice in a cycle. The multiplier-accumulator executes one multiply-add operation (32 b multiplication followed by 64 b addition) per cycle at 56.5 MHz. The area is 2.35 mm2 with 0.4 μm CMOS technology View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication

    Page(s): 1063 - 1066
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    A compact 622-Mb/s/port bit/frame synchronizer is presented. Sampling equally-phased clocks from a phase-locked loop (PLL) at the data transition edges, the bit synchronizer selects the optimum one as the extracted clock. An elastic serial-to-parallel converter is used for the frame synchronization. The circuit is designed for a 32-port ATM switch chip, achieving 622-Mb/s port capacity by four parallel 156-Mb/s bits. Using 0.5-μm CMOS technology, the circuit was verified by simulations. The bit synchronizer consumes only 15 mW under typical conditions View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An optoelectronic CMOS circuit implementing a simulated annealing algorithm

    Page(s): 1046 - 1050
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    An original optoelectronic implementation of simulated annealing is presented. A compact and simple optical system provides a chip with arrays of independent random noise sources. The silicon chip is composed of a mesh of computing cells. Each cell includes both analog and digital circuits and includes two photosensors. A detailed analysis of this cell is given including a presentation of the design constraints. A 4×4-cells prototype chip was implemented in a 1 μm CMOS digital technology and was successfully operated at 20000 iterations per second. The measurements and characterization of this chip made possible the successful design of a 600-cells chip also presented. These results demonstrate the video-rate application of simulated annealing to early vision tasks View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Micropower CMOS temperature sensor with digital output

    Page(s): 933 - 937
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    A CMOS smart temperature sensor with digital output is presented. It consumes only 7 μW. To achieve this extremely low-power consumption, the system is equipped with a facility that switches off the supply power after each sample. The circuit uses substrate bipolars as a temperature sensor. Conversion to the digital domain is done by a sigma-delta converter which makes the circuit highly insensitive to digital interference. The complete system is realized in a standard CMOS process and measures only 1.5 mm2. In the temperature range from -40 to +120°C, the inaccuracy is ±1°C after calibration at two temperatures. The circuit operates at supply voltages down to 2.2 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compact CMOS constant-gm rail-to-rail input stage with g m-control by an electronic zener diode

    Page(s): 1035 - 1040
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    A family of compact CMOS rail-to-rail input stages with constant-g m is presented. To attain a constant-gm over the whole common-mode input range, an electronic zener diode is inserted between the tails of the complementary input pairs. This zener keeps the sum of the gate-source voltages of the input pairs, and therefore the g m of the rail-to-rail input stage, constant. Two possible implementations of the zener have been realized and inserted in a rail-to-rail input stage. These input stages are implemented in two two-stage compact amplifiers. Both amplifiers have been realized in a 1 μm BiCMOS process. They have a unity-gain frequency of 2-MHz, for a capacitive load of 20 pF View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A MOS switched-capacitor ladder filter in SIMOX technology for high temperature applications up to 300°C

    Page(s): 908 - 914
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    This paper describes techniques and methods used to realize a seventh order switched-capacitor low pass filter in SIMOX technology. The filter has Bessel characteristic and a 3 dB-bandwidth of 20 Hz at a clock frequency of 100 kHz. Special design of transistors and transmission gates results in drastically reduced leakage currents at high temperatures. The power supply voltage of the switched-capacitor filter is 10 V. The temperature range is extended up to 300°C. Experimental results of the transistors, the transmission gates, the operational amplifier, and the complete filter are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver

    Page(s): 880 - 889
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1252 KB)  

    An integrated low-noise amplifier and downconversion mixer operating at 1 GHz has been fabricated for the first time in 1 μm CMOS. The overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, the IIP3 is +8 dBm, and the circuit takes 9 mA from a 3 V supply. Circuit design methods which exploit the features of CMOS well suited to these functions are in large part responsible for this performance. The front-end is also characterized in several other ways relevant to direct-conversion receivers View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A portable clock multiplier generator using digital CMOS standard cells

    Page(s): 958 - 965
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (948 KB)  

    High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs

    Page(s): 992 - 1000
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1396 KB)  

    This paper describes an efficient low-power static logic family in GaAs, called PCFL for pseudo-complementary FET logic. Its behavior mimics that of CMOS by compensating the lack of complementary transistors with the use of complementary logic signals. Like any nonratioed logic, PCFL allows the realization of complex gates. It is fully compatible with DCFL and two-phase dynamic FET Logic (TDFL). Using enhancement-mode FET's only, PCFL benefits from good process variations immunity and good noise margins. Measurement results on a ring oscillator, an inverter chain, and a frequency divider are reported. PCFL is shown to operate at 500 MHz with a 0.6 μm MESFET process. The power consumption of an inverter is about 10 μW at 100 MHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter

    Page(s): 938 - 944
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    A 175 Ms/s A/D converter with a latency of one clock cycle is designed in a 0.7 μm digital CMOS technology. The resolution of the converter is 6 b while the power dissipation is only 160 mW. The A/D converter architecture is based on a continuous time analog preprocessing topology. A continuous time current interpolation circuit is implemented. The performance of the A/D converter is ruled by a tradeoff between speed, power, and accuracy View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high resolution frequency multiplier for clock signal generation

    Page(s): 1059 - 1062
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    This paper presents a high resolution frequency multiplier (FMUL) with the ability to multiply frequency with a programmable high multiplication factor, in the order of 102-104 and of the form N/M. It was designed for chip-sets that use a real time clock (32768 Hz) for power-save operation, and an additional high-frequency oscillator, in the range of 40-60 MHz, for regular operation. Using the FMUL spares the need for the additional high-frequency oscillator. The FMUL's frequency resolution is 100 ppm, and its jitter is less than 200 ps. The circuit is designed to work with 25 V supply voltage. It is implemented in a standard 0.8 pm N-well CMOS process, and its area is 0.48 mm2 View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implementation of high peak-current IGBT gate drive circuits in VLSI compatible BiCMOS technology

    Page(s): 924 - 932
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (956 KB)  

    A BiCMOS integrated gate-drive (IGD) application specific integrated circuit (ASIC) has been implemented in a 18 V, 3 μm BiCMOS technology for insulated gate bipolar transistor- (IGBT-) based intelligent power modules (IPM). It features various monitoring and control functions such as linear dV/dt feedback and master-slave control of IGBT's, and is capable of delivering 16-18 A peak current to high capacitive loads. Classic formulas on the current capability of bipolar junction transistors (BJT's), MOSFET's, and metal conductors are briefly reviewed and additional experiments are presented in the context of our application View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CMOS low-distortion high-frequency variable-gain amplifier

    Page(s): 1029 - 1034
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    The overall system performance of mixed-signal CMOS IC's is largely determined by the dynamic performance of the analog front-ends. System features are, in contrast, mainly set by the digital architecture. In order to optimize the dynamic range of the system and to minimize the sensitivity to substrate noise, the analog-to-digital converter (ADC) has to be preceded by a variable-gain amplifier (VGA) and a differential circuit topology for the complete front-end to be adopted. Since most of present-day applications are based on single-sided signal source definitions, the differential-input VGA must be able to perform a single-to-differential signal conversion. This paper describes the principle and design of a differential CMOS low-distortion variable-gain amplifier for high-frequency (video) applications. Experimental results of the circuit show total harmonic distortion figures better than -60 dB and a gain accuracy of 0.05 dB over the -2 to +12 dB gain range for single-sided input signals View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An integrated high resolution CMOS timing generator based on an array of delay locked loops

    Page(s): 952 - 957
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 μm CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Universal low cost controller for electric motors with programmable characteristic curves

    Page(s): 1041 - 1045
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    The realization of a universal low-cost controller for electric motors in CMOS technology with programmable characteristic curves is presented. With regard to the required chip area of 2.7 mm2 in a 1.6 μm, 40 nm technology, the general advantage in comparison to microcontroller-based solutions lies in the low factory costs. The analog dc power supply is generated directly from the 230 V ac power line. An on-chip functional unit controls the firing current for the off-chip motor driving triac. Features of this functional unit are torque control and overload protection, firing, and post firing control. A new method was used to implement programmable multidimensional characteristic curves which are temperature and technology insensitive. In the actual controller application for a drilling machine motor, the mask-programmed curve shapes have been generated with the help of fuzzy algorithms. An impression of the reproducibility of multidimensional characteristic curves in manufacturing, as well as the accuracy of their precalculation, is given by introducing simulated and measured statistics of the actual design View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new asynchronous pipeline scheme: application to the design of a self-timed ring divider

    Page(s): 1001 - 1013
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1368 KB)  

    This paper describes an efficient means of synchronizing and pipelining asynchronous circuits implemented using differential cascode voltage switch logic (DCVSL) precharged function blocks. A modified version of this logic, called LDCVSL (latch differential cascode voltage switch logic), which is similar to the LCDL (latched CMOS differential logic), or DCVSL with NORA-latch, is used to improve the storage capability of the precharged function blocks. Improving the storage capability of the building blocks allows the design of an efficient pipeline scheme which is described in detail. Following a description of its potential performance, the pipeline scheme is applied to the design of self-timed rings. It is shown that more compact ring structures can be obtained without loss of performance. Our design methodology is then presented. It is based on the use of a private asynchronous standard cell library, fully compatible with an existing CMOS standard cell library provided by the foundry. Our approach allows the rapid design of standard cell based asynchronous circuits. Finally, both the pipeline scheme and design approach are illustrated through the design of a 32-b self-timed ring divider. The division algorithm is first briefly presented. The chip architecture is then described with the results obtained after fabrication. The test chip has been fabricated using the CNET/SGS-Thomson 0.5 μm three metal layer technology. The 0.7 mm2 chip computes 32-b divisions in 101 ns with a power consumption of 30 mW at a throughput of 10 million operations per second View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integrated circuit implementation of fuzzy controllers

    Page(s): 1051 - 1058
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (852 KB)  

    This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno's method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 b is achieved. The connection of these blocks according to a proposed architecture allows fuzzy chips with low silicon area whose inference speed is in the range of 2 Mega FLIPS (fuzzy logic inferences per second), View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 70 mΩ intelligent high side switch with full diagnostics

    Page(s): 915 - 923
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    A new, smart power switch for industrial, automotive, and computer applications developed in BCD (Bipolar, CMOS, DMOS) technology is described. It consists of an on-chip 70 mΩ power DMOS transistor connected in high side configuration and its driver makes the device virtually indestructible and suitable to drive any kind of load with an output current of 2.5 A. If the load is inductive, an internal voltage clamp allows fast demagnetization down to 55 V below the supply voltage. The device includes novel structures for the driver, the fully integrated charge pump circuit, and its oscillator. These circuits have specifically been designed to reduce electromagnetic interference (EMI) thanks to an accurate control of the output voltage slope and the reduction of the output voltage ripple caused by the charge pump itself. An innovative open load circuit allows the detection of the open load condition with high precision (3 mA ±10% within the temperature range from -25 to 150°C and including process spreads). Furthermore, the device protects the load from ground disconnection and is compatible with the new IEC standards concerning burst and surge tests. The quiescent current has also been reduced to 600 μA. Diagnostics for CPU feedback is externally available from the chip by two dedicated pins when the following fault conditions occur: open load, overload and short circuit to ground or to the supply voltage, overtemperature, and undervoltage supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan